| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 111 enum ImmTy { enum in __anon568464980111::AMDGPUOperand
192 ImmTy Type;
346 bool isImmTy(ImmTy ImmT) const { in isImmTy()
898 ImmTy getImmTy() const { in getImmTy()
1023 static void printImmTy(raw_ostream& OS, ImmTy Type) { in printImmTy()
1107 ImmTy Type = ImmTyNone, in CreateImm()
1354 using OptionalImmIndexMap = std::map<AMDGPUOperand::ImmTy, unsigned>;
1542 AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,
1548 AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,
1553 AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 1923 SDNode Imm, ValueType ImmTy,
1935 // immediates via explicit cast to ImmTy.
1938 (Intr Int32Regs:$src, (ImmTy Imm:$b))>;
1941 (Intr Int64Regs:$src, (ImmTy Imm:$b))>;
1946 SDNode Imm, ValueType ImmTy,
1960 (Intr Int32Regs:$src, (ImmTy Imm:$b), regclass:$c)>;
1963 (Intr Int64Regs:$src, (ImmTy Imm:$b), regclass:$c)>;
1966 (Intr Int32Regs:$src, regclass:$b, (ImmTy Imm:$c))>;
1969 (Intr Int64Regs:$src, regclass:$b, (ImmTy Imm:$c))>;
1973 (Intr Int32Regs:$src, (ImmTy Imm:$b), (ImmTy Imm:$c))>;
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/AsmPrinter/ |
| D | AsmPrinter.cpp | 1160 Type *ImmTy = Op.getFPImm()->getType(); in emitDebugValueComment() local
1161 if (ImmTy->isBFloatTy() || ImmTy->isHalfTy() || ImmTy->isFloatTy() || in emitDebugValueComment()
1162 ImmTy->isDoubleTy()) { in emitDebugValueComment()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 1181 string ImmTy = "AMDGPUOperand::ImmTy"#Name;
1184 "return parseIntWithPrefix(\""#Prefix#"\", Operands, "#ImmTy#", "#
1194 string ImmTy = "AMDGPUOperand::ImmTy"#Name;
1197 "return parseNamedBit(\""#Id#"\", Operands, "#ImmTy#"); }";
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3207 Format f, InstrItinClass itin, Operand ImmTy,
3210 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3214 Format f, InstrItinClass itin, Operand ImmTy,
3217 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3225 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3228 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3230 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3235 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3238 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3241 (i32 ImmTy:$SIMM))))]>;
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 205 struct ImmTy { struct
212 struct ImmTy Imm;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 1214 …s sve_masked_gather_x2_unscaled<ValueType Ty, SDPatternOperator Load, string Inst, Operand ImmTy> {
1216 def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), (i64 ImmTy:$imm), (nxv2i64 ZPR:$ptrs))),
1217 (!cast<Instruction>(Inst # _IMM) PPR:$gp, ZPR:$ptrs, ImmTy:$imm)>;
1405 …sve_masked_scatter_x2_unscaled<ValueType Ty, SDPatternOperator Store, string Inst, Operand ImmTy> {
1407 def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), (i64 ImmTy:$imm), (nxv2i64 ZPR:$ptrs)),
1408 (!cast<Instruction>(Inst # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, ImmTy:$imm)>;
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| D | SVEInstrFormats.td | 453 ValueType vt2, Operand ImmTy, Instruction inst>
454 : Pat<(vtd (op vt1:$Op1, (vt2 ImmTy:$Op2))),
455 (inst $Op1, ImmTy:$Op2)>;
458 ValueType vt2, ValueType vt3, Operand ImmTy,
460 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, (vt3 ImmTy:$Op3))),
461 (inst $Op1, $Op2, ImmTy:$Op3)>;
465 Operand ImmTy, Instruction inst>
466 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3, (vt4 ImmTy:$Op4))),
467 (inst $Op1, $Op2, $Op3, ImmTy:$Op4)>;
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 1495 LLT ImmTy = MRI.getType(MI.getOperand(2).getReg()); in applyShiftImmedChain() local
1496 Register NewImm = Builder.buildConstant(ImmTy, Imm).getReg(0); in applyShiftImmedChain()
|