| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 704 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
737 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
745 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
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| D | README_ALTIVEC.txt | 314 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
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| D | PPCISelLowering.cpp | 854 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in PPCTargetLowering()
937 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in PPCTargetLowering()
1185 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in PPCTargetLowering()
1186 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in PPCTargetLowering()
1287 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
1288 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
1289 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
1290 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
1292 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in PPCTargetLowering()
1293 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in PPCTargetLowering()
[all …]
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 523 INSERT_VECTOR_ELT, enumerator
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 432 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
436 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
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| D | LegalizeVectorTypes.cpp | 61 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
965 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
1719 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
1723 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
3898 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
4232 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, in CollectOpsToWiden()
5085 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT()
6533 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE()
6570 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE_SEQ()
6710 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
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| D | SelectionDAGDumper.cpp | 295 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; in getOperationName()
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| D | LegalizeDAG.cpp | 3058 case ISD::INSERT_VECTOR_ELT: in ExpandNode()
4488 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { in PromoteNode()
4989 case ISD::INSERT_VECTOR_ELT: { in PromoteNode()
5032 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT, in PromoteNode()
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| D | LegalizeIntegerTypes.cpp | 118 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerResult()
1645 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerOperand()
4828 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; in ExpandIntegerOperand()
5603 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, in PromoteIntRes_INSERT_VECTOR_ELT()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 148 setOperationAction(ISD::INSERT_VECTOR_ELT, in R600TargetLowering()
202 ISD::SELECT_CC, ISD::INSERT_VECTOR_ELT, ISD::LOAD}); in R600TargetLowering()
402 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
665 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1769 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
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| D | SIISelLowering.cpp | 274 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
304 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
305 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
318 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
319 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v6i32); in SITargetLowering()
332 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
333 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v8i32); in SITargetLowering()
346 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
347 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v16i32); in SITargetLowering()
360 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
[all …]
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| /openbsd/src/gnu/llvm/llvm/utils/ |
| D | update_mir_test_checks.py | 301 INSERT_VECTOR_ELT='IVEC',
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| /openbsd/src/gnu/llvm/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 318 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
335 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalPackedVT, Custom); in initVPUActions()
1842 return CDAG.getNode(ISD::INSERT_VECTOR_ELT, ResultVT, {AccuV, ElemV, IdxV}); in lowerBUILD_VECTOR()
1918 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
3169 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); in lowerINSERT_VECTOR_ELT()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 171 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
253 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
333 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom); in addMVEVectorTypes()
396 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
445 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
1015 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, in ARMTargetLowering()
2213 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
2227 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
4547 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue, in LowerFormalArguments()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 151 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::f16, Custom); in initializeHVXLowering()
232 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
389 setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
1787 SDValue T0 = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in LowerHvxInsertElement()
3206 case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG); in LowerHvxOperation()
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| D | HexagonISelLowering.cpp | 1643 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, in HexagonTargetLowering()
1692 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
3338 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 208 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1418 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
2183 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 322 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAIntType()
376 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
1954 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2517 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 365 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
506 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in SystemZTargetLowering()
507 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in SystemZTargetLowering()
5422 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], in buildVector()
5494 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, in lowerSCALAR_TO_VECTOR()
5524 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, in lowerINSERT_VECTOR_ELT()
5795 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
6838 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) { in combineBSWAP()
6863 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecVT, in combineBSWAP()
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| D | SystemZOperators.td | 294 def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
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| D | SystemZISelDAGToDAG.cpp | 1627 case ISD::INSERT_VECTOR_ELT: { in Select()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 524 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
547 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT, in RISCVTargetLowering()
643 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT, in RISCVTargetLowering()
712 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT, in RISCVTargetLowering()
821 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
938 ISD::VECTOR_SHUFFLE, ISD::INSERT_VECTOR_ELT, in RISCVTargetLowering()
2441 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntegerViaVecVT, Vec, in lowerBUILD_VECTOR()
2457 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntegerViaVecVT, Vec, Elt, in lowerBUILD_VECTOR()
2693 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, in lowerBUILD_VECTOR()
3799 return DAG.getBitcast(VT, DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, BVT, in LowerOperation()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 964 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, in AArch64TargetLowering()
1307 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in AArch64TargetLowering()
1576 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
1768 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForStreamingSVE()
1887 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForFixedLengthSVE()
5903 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
11091 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Input.getValueType(), OpLHS, in GeneratePerfectShuffle()
11607 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()
12416 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
12449 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, NewVector, in LowerBUILD_VECTOR()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 920 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in X86TargetLowering()
1071 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in X86TargetLowering()
1072 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in X86TargetLowering()
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in X86TargetLowering()
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in X86TargetLowering()
1105 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1537 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1643 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1880 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
2003 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
[all …]
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 464 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
714 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
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