| /openbsd/src/gnu/lib/libreadline/ |
| D | USAGE | 4 Received: from arthur.INS.CWRU.Edu (root@arthur.INS.CWRU.Edu [129.22.8.215]) by odin.INS.CWRU.Edu w…
5 id UAA25349; Thu, 22 Jul 1999 20:37:54 -0400 (EDT) (from rms@gnu.org for <chet@odin.INS.CWRU.Edu>)
6 Received: from nike.ins.cwru.edu (root@nike.INS.CWRU.Edu [129.22.8.219]) by arthur.INS.CWRU.Edu wit…
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | SelectOptimize.cpp | 499 SmallPtrSet<const Instruction *, 2> INS; in convertProfitableSIGroups() local
500 INS.insert(ASI.begin(), ASI.end()); in convertProfitableSIGroups()
509 PN->addIncoming(getTrueOrFalseValue(SI, true, INS), TrueBlock); in convertProfitableSIGroups()
510 PN->addIncoming(getTrueOrFalseValue(SI, false, INS), FalseBlock); in convertProfitableSIGroups()
515 INS.erase(SI); in convertProfitableSIGroups()
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| D | CodeGenPrepare.cpp | 7001 SmallPtrSet<const Instruction *, 2> INS; in optimizeSelectInst() local
7002 INS.insert(ASI.begin(), ASI.end()); in optimizeSelectInst()
7010 PN->addIncoming(getTrueOrFalseValue(SI, true, INS), TrueBlock); in optimizeSelectInst()
7011 PN->addIncoming(getTrueOrFalseValue(SI, false, INS), FalseBlock); in optimizeSelectInst()
7016 INS.erase(SI); in optimizeSelectInst()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 657 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
665 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
674 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
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| D | MipsSEISelDAGToDAG.cpp | 247 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops); in selectAddE()
258 CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps); in selectAddE()
1027 Opcode = Mips::INS; in trySelect()
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| D | MipsInstrInfo.cpp | 856 case Mips::INS: in verifyInstruction()
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| D | MipsSchedule.td | 137 def II_INS : InstrItinClass; // Any INS instruction
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| D | MipsScheduleP5600.td | 206 def : InstRW<[P5600WriteAL2BitExt], (instrs EXT, INS)>;
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| D | MipsScheduleGeneric.td | 48 CLO, CLZ, EXT, INS, LEA_ADDiu, LUi, NOP,
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| D | MipsInstrInfo.td | 2448 def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5,
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| /openbsd/src/usr.sbin/mtrace/ |
| D | mtrace.c | 838 #define INS 1 macro
867 have |= INS; in stat_line()
897 case INS: in stat_line()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 349 // INS V[x],V[y] is a WriteV.
359 // INS V[x],R
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| D | AArch64SchedTSV110.td | 673 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(DUP|INS)v.+lane")>;
681 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^(INS|DUP)v.+gpr")>;
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| D | AArch64InstrInfo.td | 5704 // AdvSIMD INS/DUP instructions
5869 defm INS : SIMDIns;
5997 // index type and INS extension
6024 ValueType VTScal, Instruction INS> {
6028 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
6033 (INS V128:$src, imm:$Immd,
6039 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
6047 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
6099 // INS.
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| D | AArch64InstrFormats.td | 7479 // AdvSIMD INS/DUP instructions
7768 // For all forms of the INS instruction, the "mov" mnemonic is the
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 2270 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
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