Searched refs:Hwreg (Results 1 – 21 of 21) sorted by relevance
230 .addImm(((Width - 1) << AMDGPU::Hwreg::WIDTH_M1_SHIFT_) | in insertSetreg()231 (Offset << AMDGPU::Hwreg::OFFSET_SHIFT_) | in insertSetreg()232 (AMDGPU::Hwreg::ID_MODE << AMDGPU::Hwreg::ID_SHIFT_)); in insertSetreg()279 if (((Dst & AMDGPU::Hwreg::ID_MASK_) >> AMDGPU::Hwreg::ID_SHIFT_) != in processBlockPhase1()280 AMDGPU::Hwreg::ID_MODE) in processBlockPhase1()283 unsigned Width = ((Dst & AMDGPU::Hwreg::WIDTH_M1_MASK_) >> in processBlockPhase1()284 AMDGPU::Hwreg::WIDTH_M1_SHIFT_) + in processBlockPhase1()287 (Dst & AMDGPU::Hwreg::OFFSET_MASK_) >> AMDGPU::Hwreg::OFFSET_SHIFT_; in processBlockPhase1()
471 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_LO | in emitEntryFunctionFlatScratchInit()472 (31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_))); in emitEntryFunctionFlatScratchInit()475 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_HI | in emitEntryFunctionFlatScratchInit()476 (31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_))); in emitEntryFunctionFlatScratchInit()
389 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
3587 const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg( in emitGWSMemViolTestLoop()3588 AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1); in emitGWSMemViolTestLoop()4407 AMDGPU::Hwreg::decodeHwreg(MI.getOperand(1).getImm(), ID, Offset, Width); in EmitInstrWithCustomInserter()4408 if (ID != AMDGPU::Hwreg::ID_MODE) in EmitInstrWithCustomInserter()4421 (AMDGPU::Hwreg::FP_ROUND_MASK | AMDGPU::Hwreg::FP_DENORM_MASK)) { in EmitInstrWithCustomInserter()4426 } else if (SetMask == AMDGPU::Hwreg::FP_ROUND_MASK) { in EmitInstrWithCustomInserter()4428 } else if (SetMask == AMDGPU::Hwreg::FP_DENORM_MASK) { in EmitInstrWithCustomInserter()4457 if ((SetMask & (AMDGPU::Hwreg::FP_ROUND_MASK | in EmitInstrWithCustomInserter()4458 AMDGPU::Hwreg::FP_DENORM_MASK)) == SetMask) in EmitInstrWithCustomInserter()9095 const unsigned Denorm32Reg = AMDGPU::Hwreg::ID_MODE | in LowerFDIV32()[all …]
177 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_; in getHWReg()1076 return getHWReg(TII, MI) == AMDGPU::Hwreg::ID_TRAPSTS; in checkRFEHazards()
3868 unsigned SPDenormModeBitField = AMDGPU::Hwreg::ID_MODE | in toggleSPDenormMode()3869 (4 << AMDGPU::Hwreg::OFFSET_SHIFT_) | in toggleSPDenormMode()3870 (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_); in toggleSPDenormMode()
1292 def hwreg : NamedOperandU32<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
73 namespace Hwreg { // Symbolic names for the hwreg(...) syntax.
86 namespace Hwreg { namespace
934 namespace Hwreg {
1500 namespace Hwreg { namespace
31 Hwreg Value Syntax Description
1610 using namespace llvm::AMDGPU::Hwreg; in printHwreg()
6787 using namespace llvm::AMDGPU::Hwreg; in parseHwregBody()6823 using namespace llvm::AMDGPU::Hwreg; in validateHwreg()6852 using namespace llvm::AMDGPU::Hwreg; in parseHwreg()