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Searched refs:HiHalf (Results 1 – 8 of 8) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp1043 Words[IdxW].push_back(HiHalf(W0, DAG)); in createHvxPrefixPred()
1053 Words[IdxW].push_back(HiHalf(T, DAG)); in createHvxPrefixPred()
1376 V1 = HiHalf(VecV, DAG); in insertHvxSubvectorReg()
1423 SDValue R1 = HiHalf(V, DAG); in insertHvxSubvectorReg()
2522 {HiHalf(P2, DAG), LoHalf(P1, DAG), S16}, DAG); in emitHvxMulHsV60()
2570 {HiHalf(P1, DAG), LoHalf(P1, DAG)}, DAG); in emitHvxMulLoHiV60()
2578 {HiHalf(P2, DAG), T3, S16}, DAG); in emitHvxMulLoHiV60()
2583 Hi = DAG.getNode(ISD::ADD, dl, VecTy, {HiHalf(P0, DAG), T4}); in emitHvxMulLoHiV60()
2629 SDValue Hi = HiHalf(P1, DAG); in emitHvxMulLoHiV62()
DHexagonISelDAGToDAGHVX.cpp636 return OpRef(R.OpN & (Undef | Index | HiHalf)); in hi()
653 HiHalf = 0x40000000, enumerator
654 Whole = LoHalf | HiHalf,
729 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf); in print()
1191 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf); in materialize()
DHexagonISelLowering.h463 SDValue HiHalf(SDValue V, SelectionDAG &DAG) const { in HiHalf() function
DHexagonISelLowering.cpp2672 ExtV = Off == 0 ? LoHalf(VecV, DAG) : HiHalf(VecV, DAG); in extractVector()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp1954 MachineInstr *HiHalf = in computeBase() local
1961 (void)HiHalf; in computeBase()
1962 LLVM_DEBUG(dbgs() << " "; HiHalf->dump();); in computeBase()
DSIInstrInfo.cpp6868 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp() local
6883 Worklist.insert(&HiHalf); in splitScalar64BitUnaryOp()
6941 MachineInstr *HiHalf = in splitScalar64BitAddSub() local
6960 legalizeOperands(*HiHalf, MDT); in splitScalar64BitAddSub()
7013 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp() local
7027 Worklist.insert(&HiHalf); in splitScalar64BitBinaryOp()
DSIISelLowering.cpp4132 MachineInstr *HiHalf = in EmitInstrWithCustomInserter() local
4146 TII->legalizeOperands(*HiHalf); in EmitInstrWithCustomInserter()
5752 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
5756 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf); in lowerINSERT_VECTOR_ELT()
5768 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) : in lowerINSERT_VECTOR_ELT()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsISelLowering.cpp4864 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D() local
4881 .addDef(HiHalf) in emitLDR_D()
4889 .addUse(HiHalf); in emitLDR_D()