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Searched refs:HRI (Results 1 – 20 of 20) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.cpp287 const HexagonRegisterInfo &HRI) { in needsStackFrame() argument
314 for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S) in needsStackFrame()
410 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in findShrunkPrologEpilog() local
441 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P) in findShrunkPrologEpilog()
442 for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S) in findShrunkPrologEpilog()
446 if (needsStackFrame(I, CSR, HRI)) in findShrunkPrologEpilog()
510 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in emitPrologue() local
520 insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs); in emitPrologue()
525 insertCSRRestoresInBlock(*EpilogB, CSI, HRI); in emitPrologue()
530 insertCSRRestoresInBlock(B, CSI, HRI); in emitPrologue()
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DHexagonVLIWPacketizer.cpp117 const HexagonRegisterInfo *HRI = nullptr; member in __anonaf994ad90111::HexagonPacketizer
140 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in INITIALIZE_PASS_DEPENDENCY()
213 HRI = HST.getRegisterInfo(); in runOnMachineFunction()
305 if (DepReg == HRI->getRARegister()) in isCallDependent()
309 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister()) in isCallDependent()
490 if (HII->isValidOffset(Opc, NewOff, HRI)) { in useCallersSP()
541 if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI)) in updateOffset()
664 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF); in canPromoteToNewValueStore()
714 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc); in canPromoteToNewValueStore()
726 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst); in canPromoteToNewValueStore()
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DHexagonInstrInfo.cpp135 static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) { in isDblRegForSubInst() argument
136 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
137 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
859 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in copyPhysReg() local
920 LivePhysRegs LiveAtMI(HRI); in copyPhysReg()
922 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
923 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
951 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n'; in copyPhysReg()
1054 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in expandPostRAPseudo() local
1055 LivePhysRegs LiveIn(HRI), LiveOut(HRI); in expandPostRAPseudo()
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DHexagonGenMux.cpp89 const HexagonRegisterInfo *HRI = nullptr; member in __anonc016a9790111::HexagonGenMux
147 for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I) in getSubRegs()
181 unsigned NR = HRI->getNumRegs(); in buildMaps()
349 LivePhysRegs LPR(*HRI); in genMuxInBlock()
352 for (MCSubRegIterator S(Reg, HRI, true); S.isValid(); ++S) in genMuxInBlock()
381 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction()
DHexagonVExtract.cpp104 const auto &HRI = *HST->getRegisterInfo(); in runOnMachineFunction() local
140 Align Alignment = HRI.getSpillAlign(VecRC); in runOnMachineFunction()
146 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment, in runOnMachineFunction()
161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
DHexagonBitSimplify.cpp468 auto &HRI = static_cast<const HexagonRegisterInfo&>( in parseRegSequence() local
470 unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo); in parseRegSequence()
471 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi); in parseRegSequence()
932 auto &HRI = static_cast<const HexagonRegisterInfo&>( in getFinalVRegClass() local
935 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass()
936 (void)HRI; in getFinalVRegClass()
937 assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) || in getFinalVRegClass()
938 Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi)); in getFinalVRegClass()
1083 : Transformation(true), HII(hii), HRI(hri), MRI(mri), BT(bt) {} in RedundantInstrElimination()
1098 const HexagonRegisterInfo &HRI; member in __anon0e88cdb10511::RedundantInstrElimination
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DHexagonISelDAGToDAG.h32 const HexagonRegisterInfo *HRI; variable
41 HRI(nullptr) {} in HexagonDAGToDAGISel()
47 HRI = HST->getRegisterInfo(); in runOnMachineFunction()
DHexagonConstExtenders.cpp384 const HexagonRegisterInfo *HRI = nullptr; member
446 : Rs(R), HRI(I) {} in PrintRegister()
448 const HexagonRegisterInfo &HRI; member
454 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); in operator <<()
462 : Ex(E), HRI(I) {} in PrintExpr()
464 const HexagonRegisterInfo &HRI; member
471 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); in operator <<()
480 : ExtI(EI), HRI(I) {} in PrintInit()
482 const HexagonRegisterInfo &HRI; member
488 << PrintExpr(P.ExtI.second, P.HRI) << ']'; in operator <<()
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DHexagonGenInsert.cpp568 const HexagonRegisterInfo *HRI = nullptr; member in __anonfd5032d40511::HexagonGenInsert
586 dbgs() << " " << printReg(I.first, HRI) << ":\n"; in dump_map()
589 dbgs() << " " << PrintIFR(J.first, HRI) << ", " in dump_map()
590 << PrintRegSet(J.second, HRI) << '\n'; in dump_map()
787 dbgs() << __func__ << ": " << printReg(VR, HRI) in findRecordInsertForms()
788 << " AVs: " << PrintORL(AVs, HRI) << "\n"; in findRecordInsertForms()
852 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; in findRecordInsertForms()
857 dbgs() << " (" << printReg(J.first, HRI) << ",@" << J.second << ')'; in findRecordInsertForms()
902 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) in findRecordInsertForms()
903 << ',' << printReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms()
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DHexagonBranchRelaxation.cpp70 const HexagonRegisterInfo *HRI; member
97 HRI = HST.getRegisterInfo(); in runOnMachineFunction()
DHexagonFrameLowering.h123 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
125 const HexagonRegisterInfo &HRI) const;
DHexagonOptAddrMode.cpp84 const HexagonRegisterInfo *HRI = nullptr; member in __anondc690a980111::HexagonOptAddrMode
343 return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false); in isValidOffset()
372 return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false); in isValidOffset()
863 HRI = HST.getRegisterInfo(); in runOnMachineFunction()
867 DataFlowGraph G(MF, *HII, *HRI, *MDT, MDF); in runOnMachineFunction()
DHexagonRDFOpt.cpp295 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in runOnMachineFunction() local
302 DataFlowGraph G(MF, HII, HRI, *MDT, MDF); in runOnMachineFunction()
DHexagonVLIWPacketizer.h77 const HexagonRegisterInfo *HRI; variable
DHexagonBitTracker.cpp95 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in mask() local
96 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); in mask()
136 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in composeWithSubRegIndex() local
137 bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); in composeWithSubRegIndex()
138 bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi)); in composeWithSubRegIndex()
DHexagonISelLowering.cpp460 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerCall() local
462 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT); in LowerCall()
526 Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in LowerCall()
593 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv); in LowerCall()
660 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerINLINEASM() local
661 unsigned LR = HRI.getRARegister(); in LowerINLINEASM()
1168 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerRETURNADDR() local
1188 Register Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
1194 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerFRAMEADDR() local
1202 HRI.getFrameRegister(), VT); in LowerFRAMEADDR()
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DHexagonAsmPrinter.cpp270 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); in HexagonProcessInstruction() local
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; in HexagonProcessInstruction()
DHexagonConstPropagation.cpp1888 const HexagonRegisterInfo &HRI; member in __anon98b5e5500611::HexagonConstEvaluator
1921 HRI(*Fn.getSubtarget<HexagonSubtarget>().getRegisterInfo()) { in HexagonConstEvaluator()
1954 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1955 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()
2810 dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg) in rewriteHexConstDefs()
DHexagonISelDAGToDAG.cpp1335 auto &HRI = *HST.getRegisterInfo(); in emitFunctionEntryCode() local
1336 BitVector Reserved = HRI.getReservedRegs(*MF); in emitFunctionEntryCode()
1337 for (const MCPhysReg *R = HRI.getCalleeSavedRegs(MF); *R; ++R) { in emitFunctionEntryCode()
DHexagonPatternsHVX.td96 int32_t VecSize = HRI->getSpillSize(Hexagon::HvxVRRegClass);