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Searched refs:HREAD4 (Results 1 – 25 of 127) sorted by relevance

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/openbsd/src/sys/arch/armv7/exynos/
Dexclock.c56 #define HREAD4(sc, reg) \ macro
61 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
63 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
248 reg = HREAD4(sc, EXYNOS5420_DIV_FSYS1); in exynos5420_get_frequency()
250 reg = HREAD4(sc, EXYNOS5420_SRC_FSYS); in exynos5420_get_frequency()
265 reg = HREAD4(sc, EXYNOS5420_SRC_TOP6); in exynos5420_get_frequency()
277 reg = HREAD4(sc, EXYNOS5420_RPLL_CON0); in exynos5420_get_frequency()
281 reg = HREAD4(sc, EXYNOS5420_RPLL_CON1); in exynos5420_get_frequency()
288 reg = HREAD4(sc, EXYNOS5420_SPLL_CON0); in exynos5420_get_frequency()
392 HREAD4(sc, CLOCK_APLL_CON0), 0); in exclock_get_pll_clk()
[all …]
/openbsd/src/sys/arch/riscv64/dev/
Dstfrng.c50 #define HREAD4(sc, reg) \ macro
124 stat = HREAD4(sc, RNG_STAT); in stfrng_rnd()
126 istat = HREAD4(sc, RNG_ISTAT); in stfrng_rnd()
129 enqueue_randomness(HREAD4(sc, RNG_DATA0)); in stfrng_rnd()
130 enqueue_randomness(HREAD4(sc, RNG_DATA1)); in stfrng_rnd()
131 enqueue_randomness(HREAD4(sc, RNG_DATA2)); in stfrng_rnd()
132 enqueue_randomness(HREAD4(sc, RNG_DATA3)); in stfrng_rnd()
133 enqueue_randomness(HREAD4(sc, RNG_DATA4)); in stfrng_rnd()
134 enqueue_randomness(HREAD4(sc, RNG_DATA5)); in stfrng_rnd()
135 enqueue_randomness(HREAD4(sc, RNG_DATA6)); in stfrng_rnd()
[all …]
Dmpfclock.c90 #define HREAD4(sc, reg) \ macro
144 sc->sc_clkcfg = HREAD4(sc, CLOCK_CONFIG_CR); in mpfclock_attach()
210 val = HREAD4(sc, SUBBLK_CLOCK_CR); in mpfclock_enable()
214 val = HREAD4(sc, SUBBLK_RESET_CR); in mpfclock_enable()
218 val = HREAD4(sc, SUBBLK_RESET_CR); in mpfclock_enable()
222 val = HREAD4(sc, SUBBLK_CLOCK_CR); in mpfclock_enable()
/openbsd/src/sys/dev/fdt/
Damlpciephy.c45 #define HREAD4(sc, reg) \ macro
50 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
52 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
129 reg = HREAD4(sc, PHY_R0); in amlpciephy_enable()
146 reg = HREAD4(sc, PHY_R0); in amlpciephy_enable()
199 if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) in amlpciephy_addr()
209 if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0) in amlpciephy_addr()
229 if (HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) in amlpciephy_read()
237 reg = HREAD4(sc, PHY_R5); in amlpciephy_read()
240 if ((HREAD4(sc, PHY_R5) & PHY_R5_PHY_CR_ACK) == 0) in amlpciephy_read()
[all …]
Dqcaoss.c53 #define HREAD4(sc, reg) \ macro
116 if (HREAD4(sc, AOSS_DESC_MAGIC) != AOSS_MAGIC || in qcaoss_attach()
117 HREAD4(sc, AOSS_DESC_VERSION) != AOSS_VERSION) { in qcaoss_attach()
122 sc->sc_offset = HREAD4(sc, AOSS_DESC_MCORE_MBOX_OFFSET); in qcaoss_attach()
123 sc->sc_size = HREAD4(sc, AOSS_DESC_MCORE_MBOX_SIZE); in qcaoss_attach()
130 HREAD4(sc, AOSS_DESC_UCORE_LINK_STATE)); in qcaoss_attach()
136 if (HREAD4(sc, AOSS_DESC_MCORE_LINK_STATE_ACK) == AOSS_STATE_UP) in qcaoss_attach()
149 if (HREAD4(sc, AOSS_DESC_UCORE_CH_STATE) == AOSS_STATE_UP) in qcaoss_attach()
162 if (HREAD4(sc, AOSS_DESC_MCORE_CH_STATE_ACK) == AOSS_STATE_UP) in qcaoss_attach()
200 KASSERT(HREAD4(sc, sc->sc_offset) == len); in qcaoss_send()
[all …]
Dmvrng.c48 #define HREAD4(sc, reg) \ macro
53 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
55 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
123 status = HREAD4(sc, RNG_STATUS); in mvrng_rnd()
130 detune = ~HREAD4(sc, RNG_FROENABLE) & RNG_FROENABLE_MASK; in mvrng_rnd()
138 enqueue_randomness(HREAD4(sc, RNG_OUTPUT0)); in mvrng_rnd()
139 enqueue_randomness(HREAD4(sc, RNG_OUTPUT1)); in mvrng_rnd()
140 enqueue_randomness(HREAD4(sc, RNG_OUTPUT2)); in mvrng_rnd()
141 enqueue_randomness(HREAD4(sc, RNG_OUTPUT3)); in mvrng_rnd()
Dimxrtc.c39 #define HREAD4(sc, reg) \ macro
105 cr = HREAD4(sc, LPCR); in imxrtc_gettime()
115 mr = HREAD4(sc, LPSRTCMR); in imxrtc_gettime()
116 lr = HREAD4(sc, LPSRTCLR); in imxrtc_gettime()
119 mr = HREAD4(sc, LPSRTCMR); in imxrtc_gettime()
120 lr = HREAD4(sc, LPSRTCLR); in imxrtc_gettime()
144 cr = HREAD4(sc, LPCR); in imxrtc_settime()
148 if ((HREAD4(sc, LPCR) & LPCR_SRTC_ENV) == 0) in imxrtc_settime()
160 if (HREAD4(sc, LPCR) & LPCR_SRTC_ENV) in imxrtc_settime()
Dexrtc.c41 #define HREAD4(sc, reg) \ macro
104 dt.dt_sec = FROMBCD(HREAD4(sc, RTCSEC)); in exrtc_gettime()
105 dt.dt_min = FROMBCD(HREAD4(sc, RTCMIN)); in exrtc_gettime()
106 dt.dt_hour = FROMBCD(HREAD4(sc, RTCHOUR)); in exrtc_gettime()
107 dt.dt_day = FROMBCD(HREAD4(sc, RTCDAY)); in exrtc_gettime()
108 dt.dt_mon = FROMBCD(HREAD4(sc, RTCMON)); in exrtc_gettime()
109 dt.dt_year = FROMBCD(HREAD4(sc, RTCYEAR)) + 1900; in exrtc_gettime()
112 if (dt.dt_sec > FROMBCD(HREAD4(sc, RTCSEC)) && !retried) { in exrtc_gettime()
144 val = HREAD4(sc, RTCCTRL); in exrtc_settime()
Drkiis.c131 #define HREAD4(sc, reg) \ macro
136 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
138 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
297 sr = HREAD4(sc, I2S_INTSR); in rkiis_intr()
301 val = HREAD4(sc, I2S_RXFIFOLR); in rkiis_intr()
305 *rch->ch_data = HREAD4(sc, I2S_RXDR); in rkiis_intr()
316 val = HREAD4(sc, I2S_TXFIFOLR); in rkiis_intr()
346 txcr = HREAD4(sc, I2S_TXCR); in rkiis_set_format()
347 rxcr = HREAD4(sc, I2S_RXCR); in rkiis_set_format()
348 ckr = HREAD4(sc, I2S_CKR); in rkiis_set_format()
[all …]
Damlclock.c106 #define HREAD4(sc, reg) \ macro
111 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
113 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
211 reg = HREAD4(sc, offset); in amlclock_get_cpu_freq()
255 reg = HREAD4(sc, offset); in amlclock_set_cpu_freq()
306 reg = HREAD4(sc, offset); in amlclock_set_cpu_freq()
317 reg = HREAD4(sc, offset); in amlclock_set_cpu_freq()
330 reg = HREAD4(sc, offset); in amlclock_set_cpu_freq()
337 reg = HREAD4(sc, offset); in amlclock_set_cpu_freq()
348 reg = HREAD4(sc, offset); in amlclock_set_cpu_freq()
[all …]
Dimxanatop.c91 #define HREAD4(sc, reg) \ macro
96 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
98 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
224 bit_val = HREAD4(ir->ir_sc, ir->ir_reg_offset) >> ir->ir_vol_bit_shift; in imxanatop_get_voltage()
240 reg = HREAD4(ir->ir_sc, ir->ir_reg_offset); in imxanatop_set_voltage()
249 reg = HREAD4(ir->ir_sc, ir->ir_delay_reg_offset); in imxanatop_set_voltage()
269 if (HREAD4(sc, ANALOG_PLL_ARM) in imxanatop_decode_pll()
272 div = HREAD4(sc, ANALOG_PLL_ARM) in imxanatop_decode_pll()
276 div = HREAD4(sc, ANALOG_PLL_SYS) in imxanatop_decode_pll()
280 div = HREAD4(sc, ANALOG_PLL_USB2) in imxanatop_decode_pll()
[all …]
Dimxspi.c121 #define HREAD4(sc, reg) \ macro
126 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
128 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
200 while (HREAD4(sc, SPI_STATREG) & SPI_STATREG_RR) in imxspi_attachhook()
201 HREAD4(sc, SPI_RXDATA); in imxspi_attachhook()
246 configreg = HREAD4(sc, SPI_CONFIGREG); in imxspi_config()
262 HWRITE4(sc, SPI_TESTREG, HREAD4(sc, SPI_TESTREG) & in imxspi_config()
296 state = HREAD4(sc, SPI_STATREG); in imxspi_wait_state()
298 if (((state = HREAD4(sc, SPI_STATREG)) & mask) == value) in imxspi_wait_state()
342 while (HREAD4(sc, SPI_STATREG) & SPI_STATREG_RR) in imxspi_transfer()
[all …]
Damldwusb.c105 #define HREAD4(sc, reg) \ macro
110 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
112 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
175 reg = HREAD4(sc, USB_R1); in amldwusb_attach()
182 reg = HREAD4(sc, USB_R5); in amldwusb_attach()
220 reg = HREAD4(sc, USB_R3); in amldwusb_init_usb3()
229 reg = HREAD4(sc, USB_R2); in amldwusb_init_usb3()
233 reg = HREAD4(sc, USB_R2); in amldwusb_init_usb3()
241 reg = HREAD4(sc, USB_R1); in amldwusb_init_usb3()
Dimxccm.c176 #define HREAD4(sc, reg) \ macro
181 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
183 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
361 uint32_t ccsr = HREAD4(sc, CCM_CCSR); in imxccm_get_armclk()
403 uint32_t podf = HREAD4(sc, CCM_CSCDR2); in imxccm_get_ecspiclk()
414 uint32_t cscmr1 = HREAD4(sc, CCM_CSCMR1); in imxccm_get_usdhx()
415 uint32_t cscdr1 = HREAD4(sc, CCM_CSCDR1); in imxccm_get_usdhx()
436 uint32_t podf = HREAD4(sc, CCM_CSCDR1) & CCM_CSCDR1_UART_PODF_MASK; in imxccm_get_uartclk()
444 if ((HREAD4(sc, CCM_CBCDR) >> CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) in imxccm_get_periphclk()
446 switch((HREAD4(sc, CCM_CBCMR) in imxccm_get_periphclk()
[all …]
Ddwmmc.c156 #define HREAD4(sc, reg) \ macro
161 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
163 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
321 hcon = HREAD4(sc, SDMMC_HCON); in dwmmc_attach()
340 fifoth = HREAD4(sc, SDMMC_FIFOTH); in dwmmc_attach()
393 if ((HREAD4(sc, SDMMC_CTRL) & SDMMC_CTRL_ALL_RESET) == 0) in dwmmc_attach()
552 stat = HREAD4(sc, SDMMC_IDSTS(sc)); in dwmmc_intr()
560 stat = HREAD4(sc, SDMMC_MINTSTS); in dwmmc_intr()
629 cdetect = HREAD4(sc, SDMMC_CDETECT); in dwmmc_card_detect()
682 if ((HREAD4(sc, SDMMC_CMD) & SDMMC_CMD_START_CMD) == 0) in dwmmc_bus_clock()
[all …]
Dimxpwm.c53 #define HREAD4(sc, reg) \ macro
58 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
60 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
138 prescale = ((HREAD4(sc, PWM_CR) >> PWM_CR_PRESCALER_SHIFT) & in imxpwm_get_state()
144 if (HREAD4(sc, PWM_CR) & PWM_CR_EN) in imxpwm_get_state()
147 pcycles = HREAD4(sc, PWM_PR); in imxpwm_get_state()
155 dcycles = HREAD4(sc, PWM_SAR); in imxpwm_get_state()
195 if ((HREAD4(sc, PWM_CR) & PWM_CR_SWR) == 0) in imxpwm_set_state()
Drkcomphy.c99 #define HREAD4(sc, reg) \ macro
104 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
106 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
176 reg = HREAD4(sc, COMBO_PIPE_PHY_REG(32)); in rkcomphy_rk3568_pll_tune()
183 reg = HREAD4(sc, COMBO_PIPE_PHY_REG(5)); in rkcomphy_rk3568_pll_tune()
226 reg = HREAD4(sc, COMBO_PIPE_PHY_REG(31)); in rkcomphy_rk3568_enable()
234 reg = HREAD4(sc, COMBO_PIPE_PHY_REG(14)); in rkcomphy_rk3568_enable()
277 reg = HREAD4(sc, COMBO_PIPE_PHY_REG(14)); in rkcomphy_rk3568_enable()
281 reg = HREAD4(sc, COMBO_PIPE_PHY_REG(15)); in rkcomphy_rk3568_enable()
299 reg = HREAD4(sc, COMBO_PIPE_PHY_REG(31)); in rkcomphy_rk3568_enable()
[all …]
Dmvclock.c31 #define HREAD4(sc, reg) \ macro
36 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
38 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
414 reg = HREAD4(sc, PERIPH_CLK_DIS); in a3700_periph_enable()
426 reg = HREAD4(sc, PERIPH_TBG_SEL); in a3700_periph_tbg_get_frequency()
436 uint32_t reg = HREAD4(sc, off); in a3700_periph_get_div()
444 uint32_t reg = HREAD4(sc, off); in a3700_periph_get_double_div()
480 vcodiv = HREAD4(sc, TBG_CTRL8); in a3700_tbg_get_frequency()
485 vcodiv = HREAD4(sc, TBG_CTRL8); in a3700_tbg_get_frequency()
490 vcodiv = HREAD4(sc, TBG_CTRL1); in a3700_tbg_get_frequency()
[all …]
Dsxirsb.c60 #define HREAD4(sc, reg) \ macro
65 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
67 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
188 if ((HREAD4(sc, RSB_CTRL) & RSB_CTRL_SOFT_RESET) == 0) in sxirsb_init()
215 if ((HREAD4(sc, RSB_DMCR) & RSB_DMCR_DEVICE_MODE_START) == 0) in sxirsb_init()
235 if ((HREAD4(sc, RSB_CTRL) & RSB_CTRL_START_TRANS) == 0) in sxirsb_init()
286 if ((HREAD4(sc, RSB_CTRL) & RSB_CTRL_START_TRANS) == 0) in sxirsb_do_trans()
290 stat = HREAD4(sc, RSB_STAT); in sxirsb_do_trans()
314 return HREAD4(sc, RSB_DATA); in rsb_read_1()
332 return HREAD4(sc, RSB_DATA); in rsb_read_2()
Drkiic.c69 #define HREAD4(sc, reg) \ macro
74 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
76 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
207 if (HREAD4(sc, RKI2C_IPD) & RKI2C_IPD_START) in rkiic_send_start()
226 if (HREAD4(sc, RKI2C_IPD) & RKI2C_IPD_STOP) in rkiic_send_stop()
264 if (HREAD4(sc, RKI2C_IPD) & RKI2C_IPD_MBTF) in rkiic_write()
303 if (HREAD4(sc, RKI2C_IPD) & RKI2C_IPD_MBRF) in rkiic_read()
315 rxdata = HREAD4(sc, RKI2C_RXDATA0 + i); in rkiic_read()
325 con = HREAD4(sc, RKI2C_CON); in rkiic_read()
349 con = HREAD4(sc, RKI2C_CON); in rkiic_exec()
Drkpwm.c44 #define HREAD4(sc, reg) \ macro
49 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
51 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
135 cycles = HREAD4(sc, PWM_V2_PERIOD); in rkpwm_get_state()
136 act_cycles = HREAD4(sc, PWM_V2_DUTY); in rkpwm_get_state()
141 if (HREAD4(sc, PWM_V2_CTRL) & PWM_V2_CTRL_ENABLE) in rkpwm_get_state()
/openbsd/src/sys/arch/armv7/omap/
Domrng.c55 #define HREAD4(sc, reg) \ macro
60 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
62 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
136 status = HREAD4(sc, RNG_STATUS); in omrng_rnd()
143 detune = ~HREAD4(sc, RNG_FROENABLE) & RNG_FROENABLE_MASK; in omrng_rnd()
151 enqueue_randomness(HREAD4(sc, RNG_OUTPUT0)); in omrng_rnd()
152 enqueue_randomness(HREAD4(sc, RNG_OUTPUT1)); in omrng_rnd()
Dommmc.c221 #define HREAD4(sc, reg) \ macro
226 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
228 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
366 caps = HREAD4(sc, MMCHS_CAPA); in ommmc_attach()
428 " trying 512\n", HREAD4(sc, MMCHS_CAPA)); in ommmc_attach()
610 return !ISSET(HREAD4(sc, MMCHS_SYSTEST), MMCHS_SYSTEST_SDCD) ? in ommmc_card_detect()
661 reg = HREAD4(sc, MMCHS_HCTL); in ommmc_bus_power()
674 if (!ISSET(HREAD4(sc, MMCHS_HCTL), MMCHS_HCTL_SDBP)) { in ommmc_bus_power()
721 if (!ISSET(HREAD4(sc, MMCHS_PSTATE), in ommmc_bus_clock()
746 reg = HREAD4(sc, MMCHS_SYSCTL); in ommmc_bus_clock()
[all …]
/openbsd/src/sys/arch/arm64/dev/
Daplpmgr.c43 #define HREAD4(sc, reg) \ macro
183 val = HREAD4(sc, ps->ps_offset); in aplpmgr_enable()
189 val = HREAD4(sc, ps->ps_offset); in aplpmgr_enable()
211 val = HREAD4(sc, ps->ps_offset); in aplpmgr_reset()
214 val = HREAD4(sc, ps->ps_offset); in aplpmgr_reset()
218 val = HREAD4(sc, ps->ps_offset); in aplpmgr_reset()
221 val = HREAD4(sc, ps->ps_offset); in aplpmgr_reset()
Daplnco.c42 #define HREAD4(sc, reg) \ macro
47 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
49 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
180 div = HREAD4(sc, NCO_DIV(idx)); in aplnco_get_frequency()
187 inc1 = HREAD4(sc, NCO_INC1(idx)); in aplnco_get_frequency()
188 inc2 = HREAD4(sc, NCO_INC2(idx)); in aplnco_get_frequency()
227 ctrl = HREAD4(sc, NCO_CTRL(idx)); in aplnco_set_frequency()

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