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Searched refs:GENMASK (Results 1 – 25 of 50) sorted by relevance

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/openbsd/src/sys/dev/ic/
Dqwxreg.h126 #define WMI_TLV_LEN GENMASK(15, 0)
127 #define WMI_TLV_TAG GENMASK(31, 16)
130 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)
2557 #define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1)
3351 #define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0)
3538 #define WMI_CHAN_INFO_MODE GENMASK(5, 0)
3553 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0)
3554 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8)
3555 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16)
3556 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24)
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Dqwzreg.h122 #define WMI_TLV_LEN GENMASK(15, 0)
123 #define WMI_TLV_TAG GENMASK(31, 16)
126 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)
2628 #define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1)
3418 #define WMI_SCAN_DWELL_MODE_MASK GENMASK(23, 21)
3600 #define WMI_CHAN_INFO_MODE GENMASK(5, 0)
3615 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0)
3616 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8)
3617 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16)
3618 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24)
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Dqwzvar.h513 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
514 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
1009 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
1010 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
1015 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
1016 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
1017 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
1066 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0)
1067 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
1069 #define DP_REO_QREF_NUM GENMASK(31, 16)
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Dqwxvar.h512 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
513 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
992 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
993 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
998 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
999 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
1000 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
/openbsd/src/sys/dev/pci/drm/i915/gt/uc/
Dguc_capture_fwif.h71 #define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0)
115 #define CAP_HDR_CAPTURE_VFID GENMASK(7, 0)
117 #define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */
118 #define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */
119 #define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8)
123 #define CAP_HDR_NUM_MMIOS GENMASK(9, 0)
139 #define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0)
141 #define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0)
142 #define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */
Dintel_guc_fwif.h67 #define WQ_TYPE_MASK GENMASK(7, 0)
68 #define WQ_LEN_MASK GENMASK(26, 16)
70 #define WQ_GUC_ID_MASK GENMASK(15, 0)
71 #define WQ_RING_TAIL_MASK GENMASK(28, 18)
377 #define GUC_REGSET_STEERING_GROUP GENMASK(15, 12)
378 #define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20)
Dintel_gsc_binary_headers.h72 #define INTEL_GSC_BPDT_ENTRY_TYPE_MASK GENMASK(15, 0)
102 #define INTEL_GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)
Dintel_gsc_proxy.c58 #define GSC_PROXY_TYPE GENMASK(7, 0)
59 #define GSC_PROXY_PAYLOAD_LENGTH GENMASK(31, 16)
/openbsd/src/sys/dev/pci/
Dif_mwxreg.h97 #define MT_WTBL_LMAC_ID GENMASK(14, 8)
98 #define MT_WTBL_LMAC_DW GENMASK(7, 2)
108 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
673 #define MT_TXD3_SEQ GENMASK(27, 16)
676 #define MT_TXD3_TX_COUNT GENMASK(10, 6)
715 #define MT_TXD7_PSE_FID GENMASK(27, 16)
716 #define MT_TXD7_SPE_IDX GENMASK(15, 11)
811 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
813 #define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
814 #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
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Dif_qwz_pci.c86 #define GENMASK(h, l) (((~0UL) >> (BITS_PER_LONG - (h) - 1)) & ((~0UL) << (l))) macro
116 #define ATH12K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
118 #define ATH12K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
119 #define ATH12K_PCI_WINDOW_STATIC_MASK GENMASK(31, 6)
125 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
126 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
185 #define MHI_CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
192 #define MHI_CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
196 #define MHI_CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
197 #define MHI_CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
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Dif_qwx_pci.c86 #define GENMASK(h, l) (((~0UL) >> (BITS_PER_LONG - (h) - 1)) & ((~0UL) << (l))) macro
116 #define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
118 #define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
124 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
125 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
181 #define MHI_CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
188 #define MHI_CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
192 #define MHI_CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
193 #define MHI_CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
204 #define MHI_EV_CTX_RESERVED_MASK GENMASK(7, 0)
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/openbsd/src/sys/dev/pci/drm/i915/gvt/
Dcmd_parser.c395 FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
1036 (cmd_val(s, i) & GENMASK(22, 2))
1039 (cmd_val(s, i) & GENMASK(22, 18))
1042 (cmd_val(s, i) & GENMASK(31, 2))
1045 (cmd_val(s, i) & GENMASK(15, 0))
1204 gma = cmd_val(s, 2) & GENMASK(31, 3); in cmd_handler_pipe_control()
1305 v = (dword0 & GENMASK(21, 19)) >> 19; in gen8_decode_mi_display_flip()
1312 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; in gen8_decode_mi_display_flip()
1314 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; in gen8_decode_mi_display_flip()
1315 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); in gen8_decode_mi_display_flip()
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Dgvt.h484 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); in intel_vgpu_write_pci_bar()
/openbsd/src/sys/dev/pci/drm/i915/
Di915_reg_defs.h48 ((u32)(GENMASK(__high, __low) + \
78 ((u8)(GENMASK(__high, __low) + \
171 ((u16)(GENMASK(__high, __low) + \
Di915_params.h35 #define ENABLE_GUC_MASK GENMASK(1, 0)
Dintel_wakeref.h163 GENMASK(BITS_PER_LONG - 1, __INTEL_WAKEREF_PUT_LAST_BIT__) in __intel_wakeref_put()
/openbsd/src/sys/dev/pci/drm/
Ddrm_displayid_internal.h132 #define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
133 #define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
Ddrm_panic.c177 return pix | GENMASK(31, 24); /* fill alpha bits */ in convert_xrgb8888_to_argb8888()
193 GENMASK(31, 24); /* fill alpha bits */ in convert_xrgb8888_to_abgr8888()
209 return GENMASK(31, 30) /* set alpha bits */ | pix | ((pix >> 8) & 0x00300C03); in convert_xrgb8888_to_argb2101010()
217 return GENMASK(31, 30) /* set alpha bits */ | pix | ((pix >> 8) & 0x00300C03); in convert_xrgb8888_to_abgr2101010()
Ddrm_format_helper.c722 pix |= GENMASK(31, 24); /* fill alpha bits */ in drm_fb_xrgb8888_to_argb8888_line()
774 GENMASK(31, 24); /* fill alpha bits */ in drm_fb_xrgb8888_to_abgr8888_line()
891 pix = GENMASK(31, 30) | /* set alpha bits */ in drm_fb_xrgb8888_to_argb2101010_line()
/openbsd/src/sys/dev/pci/drm/i915/gt/
Dintel_lrc.h90 #define CTX_GTT_ADDRESS_MASK GENMASK(31, 12)
97 #define GEN12_CTX_PRIORITY_MASK GENMASK(10, 9)
Dintel_gpu_commands.h232 #define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)
244 #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
Dselftest_lrc.c31 #define LRI_LENGTH_MASK GENMASK(7, 0)
208 if ((lri & GENMASK(31, 23)) != LRI_HEADER) { in live_lrc_layout()
1013 if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) { in store_context()
1173 if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) { in load_context()
1326 if ((hw[dw] & GENMASK(31, 23)) != LRI_HEADER) { in compare_isolation()
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfxhub_v1_2.c70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_setup_vm_pt_regs()
433 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_enable()
474 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_gart_disable()
532 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_set_fault_enable_default()
581 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_init()
/openbsd/src/sys/dev/pci/drm/i915/display/
Dintel_frontbuffer.h68 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
/openbsd/src/sys/dev/pci/drm/include/linux/
Dbitops.h33 #define GENMASK(h, l) (((~0UL) >> (BITS_PER_LONG - (h) - 1)) & ((~0UL) << (l))) macro

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