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Searched refs:GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK (Results 1 – 6 of 6) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_sh_mask.h21307 #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK … macro
Dgc_11_0_0_sh_mask.h25224 #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK … macro
Dgc_12_0_0_sh_mask.h14266 #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK … macro
Dgc_11_0_3_sh_mask.h27729 #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK … macro
Dgc_10_1_0_sh_mask.h11720 #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK … macro
Dgc_10_3_0_sh_mask.h11231 #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK … macro