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Searched refs:FIELD_GET (Results 1 – 19 of 19) sorted by relevance

/openbsd/src/sys/dev/pci/drm/i915/gt/uc/
Dintel_guc_ct.c497 FIELD_GET(GUC_HXG_EVENT_MSG_0_ACTION, action[0])); in ct_write()
555 FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \ in wait_for_ct_request_update()
676 FIELD_GET(INTEL_GUC_CT_SEND_G2H_DW_MASK, f_) ? \
677 FIELD_GET(INTEL_GUC_CT_SEND_G2H_DW_MASK, f_) + \
796 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) { in ct_send()
798 FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, *status)); in ct_send()
803 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) != GUC_HXG_TYPE_RESPONSE_SUCCESS) { in ct_send()
810 WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, request.status)); in ct_send()
817 err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status); in ct_send()
953 len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, header) + GUC_CTB_MSG_MIN_LEN; in ct_read()
[all …]
Dintel_guc.c507 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST); in intel_guc_send_mmio()
508 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST); in intel_guc_send_mmio()
538 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) { in intel_guc_send_mmio()
540 FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \ in intel_guc_send_mmio()
541 FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; }) in intel_guc_send_mmio()
546 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != in intel_guc_send_mmio()
552 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) { in intel_guc_send_mmio()
553 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); in intel_guc_send_mmio()
560 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) { in intel_guc_send_mmio()
561 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); in intel_guc_send_mmio()
[all …]
Dintel_guc_capture.c1175 is_partial = FIELD_GET(CAP_GRP_HDR_CAPTURE_TYPE, ghdr.info); in guc_capture_extract_reglists()
1176 numlists = FIELD_GET(CAP_GRP_HDR_NUM_CAPTURES, ghdr.info); in guc_capture_extract_reglists()
1184 datatype = FIELD_GET(CAP_HDR_CAPTURE_TYPE, hdr.info); in guc_capture_extract_reglists()
1187 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); in guc_capture_extract_reglists()
1235 node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner); in guc_capture_extract_reglists()
1238 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); in guc_capture_extract_reglists()
1239 node->eng_inst = FIELD_GET(CAP_HDR_ENGINE_INSTANCE, hdr.info); in guc_capture_extract_reglists()
1244 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); in guc_capture_extract_reglists()
1250 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); in guc_capture_extract_reglists()
1490 FIELD_GET(GUC_REGSET_STEERING_GROUP, regs[j].flags), in intel_guc_capture_print_engine_node()
[all …]
Dintel_gsc_proxy.c161 u32 type = FIELD_GET(GSC_PROXY_TYPE, header->hdr); in validate_proxy_header()
162 u32 length = FIELD_GET(GSC_PROXY_PAYLOAD_LENGTH, header->hdr); in validate_proxy_header()
218 if (FIELD_GET(GSC_PROXY_TYPE, to_csme->proxy_header.hdr) == in proxy_query()
Dintel_uc_fw.c585 ver->major = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, css_value); in uc_unpack_css_version()
586 ver->minor = FIELD_GET(CSS_SW_VERSION_UC_MINOR, css_value); in uc_unpack_css_version()
587 ver->patch = FIELD_GET(CSS_SW_VERSION_UC_PATCH, css_value); in uc_unpack_css_version()
/openbsd/src/sys/dev/pci/drm/i915/
Di915_reg_defs.h132 #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
144 #define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
261 #define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
Dintel_wakeref.c81 FIELD_GET(INTEL_WAKEREF_PUT_DELAY, flags)); in __intel_wakeref_put_last()
/openbsd/src/sys/dev/ic/
Dqwx.c98 #define FIELD_GET(_m, _v) ((typeof(_m))(((_v) & (_m)) >> __bf_shf(_m))) macro
1229 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, in qwx_hw_ipq8074_rx_desc_get_first_msdu()
1236 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, in qwx_hw_ipq8074_rx_desc_get_l3_pad_bytes()
1256 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, in qwx_hw_ipq8074_rx_desc_get_encrypt_type()
1263 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, in qwx_hw_ipq8074_rx_desc_get_decap_type()
1270 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, in qwx_hw_ipq8074_rx_desc_get_mesh_ctl()
1277 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, in qwx_hw_ipq8074_rx_desc_get_ldpc_support()
1284 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, in qwx_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld()
1291 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, in qwx_hw_ipq8074_rx_desc_get_mpdu_fc_valid()
1298 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, in qwx_hw_ipq8074_rx_desc_get_mpdu_start_seq_no()
[all …]
Dqwz.c98 #define FIELD_GET(_m, _v) ((typeof(_m))(((_v) & (_m)) >> __bf_shf(_m))) macro
1061 return !!FIELD_GET(RX_MSDU_END_INFO5_FIRST_MSDU, in qwz_hw_wcn7850_rx_desc_get_first_msdu()
1068 return !!FIELD_GET(RX_MSDU_END_INFO5_LAST_MSDU, in qwz_hw_wcn7850_rx_desc_get_last_msdu()
1075 return FIELD_GET(RX_MSDU_END_INFO5_L3_HDR_PADDING, in qwz_hw_wcn7850_rx_desc_get_l3_pad_bytes()
1082 return !!FIELD_GET(RX_MPDU_START_INFO4_ENCRYPT_INFO_VALID, in qwz_hw_wcn7850_rx_desc_encrypt_valid()
1089 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, in qwz_hw_wcn7850_rx_desc_get_encrypt_type()
1096 return FIELD_GET(RX_MSDU_END_INFO11_DECAP_FORMAT, in qwz_hw_wcn7850_rx_desc_get_decap_type()
1103 return FIELD_GET(RX_MSDU_END_INFO11_MESH_CTRL_PRESENT, in qwz_hw_wcn7850_rx_desc_get_mesh_ctl()
1110 return !!FIELD_GET(RX_MPDU_START_INFO4_MPDU_SEQ_CTRL_VALID, in qwz_hw_wcn7850_rx_desc_get_mpdu_seq_ctl_vld()
1117 return !!FIELD_GET(RX_MPDU_START_INFO4_MPDU_FCTRL_VALID, in qwz_hw_wcn7850_rx_desc_get_mpdu_fc_valid()
[all …]
Dqwzreg.h2627 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val)
2630 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val)
3063 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3])
3066 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4])
3069 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4])
3072 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2])
3075 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2])
8220 (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val)))
13372 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
13374 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
[all …]
Dqwxreg.h2556 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val)
2559 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val)
2992 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3])
2995 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4])
2998 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4])
3001 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2])
3004 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2])
7961 (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val)))
12841 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
12843 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
[all …]
/openbsd/src/sys/dev/pci/drm/include/linux/
Dbitfield.h11 #define FIELD_GET(_m, _v) \ macro
/openbsd/src/sys/dev/pci/
Dif_mwx.c4330 fc = htole16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); in mt7921_mac_fill_rx()
4331 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); in mt7921_mac_fill_rx()
4332 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); in mt7921_mac_fill_rx()
4341 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { in mt7921_mac_fill_rx()
4416 stbc = FIELD_GET(MT_PRXV_STBC, v0); in mt7921_mac_fill_rx()
4417 gi = FIELD_GET(MT_PRXV_SGI, v0); in mt7921_mac_fill_rx()
4420 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); in mt7921_mac_fill_rx()
4421 mode = FIELD_GET(MT_PRXV_TX_MODE, v0); in mt7921_mac_fill_rx()
4438 FIELD_GET(MT_PRXV_NSTS, v0) + 1; in mt7921_mac_fill_rx()
4448 FIELD_GET(MT_PRXV_NSTS, v0) + 1; in mt7921_mac_fill_rx()
[all …]
Dif_qwx_pci.c88 #define FIELD_GET(_m, _v) ((typeof(_m))(((_v) & (_m)) >> __bf_shf(_m))) macro
1447 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, soc_hw_version); in qwx_pci_read_hw_version()
1448 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, soc_hw_version); in qwx_pci_read_hw_version()
1797 uint32_t window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset); in qwx_pci_select_window()
1866 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET); in qwx_pci_select_static_window()
1867 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE); in qwx_pci_select_static_window()
Dif_qwz_pci.c88 #define FIELD_GET(_m, _v) ((typeof(_m))(((_v) & (_m)) >> __bf_shf(_m))) macro
1327 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, soc_hw_version); in qwz_pci_read_hw_version()
1328 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, soc_hw_version); in qwz_pci_read_hw_version()
1678 uint32_t window = FIELD_GET(ATH12K_PCI_WINDOW_VALUE_MASK, offset); in qwz_pci_select_window()
1773 umac_window = FIELD_GET(ATH12K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET); in qwz_pci_select_static_window()
1774 ce_window = FIELD_GET(ATH12K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE); in qwz_pci_select_static_window()
Dif_mwxreg.h1406 #define rcpi_to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
/openbsd/src/sys/dev/pci/drm/i915/gt/
Dintel_execlists_submission.c159 (FIELD_GET(GEN12_CSB_SW_CTX_ID_MASK, csb_dw) != GEN12_IDLE_CTX_ID)
165 (FIELD_GET(XEHP_CSB_SW_CTX_ID_MASK, csb_dw) != XEHP_IDLE_CTX_ID)
/openbsd/src/sys/dev/pci/drm/
Ddrm_edid.c6579 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { in drm_parse_vesa_mso_data()
6600 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); in drm_parse_vesa_mso_data()
/openbsd/src/sys/dev/pci/drm/i915/gvt/
Dcmd_parser.c395 FIELD_GET(GENMASK(end, start), cmd_val(s, dword))