Searched refs:FCR (Results 1 – 12 of 12) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/DebugInfo/CodeView/ |
| D | StringsAndChecksums.cpp | 71 const DebugSubsectionRecord &FCR) { in initializeChecksums() argument
72 assert(FCR.kind() == DebugSubsectionKind::FileChecksums); in initializeChecksums()
77 consumeError(OwnedChecksums->initialize(FCR.getRecordData())); in initializeChecksums()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/DebugInfo/CodeView/ |
| D | StringsAndChecksums.h | 74 void initializeChecksums(const DebugSubsectionRecord &FCR);
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| /openbsd/src/gnu/usr.bin/binutils/opcodes/ |
| D | ia64-waw.tbl | 10 AR[FCR]; mov-to-AR-FCR; mov-to-AR-FCR; impliedF
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| D | ia64-ic.tbl | 78 mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR]
144 mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR]
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| D | ia64-raw.tbl | 10 AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF
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| D | ChangeLog-0203 | 975 (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
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| /openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/ |
| D | ia64-ic.tbl | 78 mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR]
145 mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR]
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| D | ia64-waw.tbl | 10 AR[FCR]; IC:mov-to-AR-FCR; IC:mov-to-AR-FCR; impliedF
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| D | ia64-raw.tbl | 10 AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF
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| D | ChangeLog-0203 | 975 (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 199 def FCR#I : MipsReg<I, ""#I>;
423 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 10252 std::optional<FPValueAndVReg> FCR; in isCanonicalized() local
10254 if (mi_match(Reg, MRI, MIPatternMatch::m_GFCstOrSplat(FCR))) { in isCanonicalized()
10255 if (FCR->Value.isSignaling()) in isCanonicalized()
10257 return !FCR->Value.isDenormal() || in isCanonicalized()
10258 denormalsEnabledForType(MRI.getType(FCR->VReg), MF); in isCanonicalized()
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