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/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrConv.td58 defm I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
59 [(set I32:$dst, (fp_to_sint F32:$src))],
63 defm I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
64 [(set I32:$dst, (fp_to_uint F32:$src))],
68 defm I64_TRUNC_S_SAT_F32 : I<(outs I64:$dst), (ins F32:$src), (outs), (ins),
69 [(set I64:$dst, (fp_to_sint F32:$src))],
73 defm I64_TRUNC_U_SAT_F32 : I<(outs I64:$dst), (ins F32:$src), (outs), (ins),
74 [(set I64:$dst, (fp_to_uint F32:$src))],
100 def : Pat<(fp_to_sint_sat F32:$src, i32), (I32_TRUNC_S_SAT_F32 F32:$src)>;
101 def : Pat<(fp_to_uint_sat F32:$src, i32), (I32_TRUNC_U_SAT_F32 F32:$src)>;
[all …]
DWebAssemblyInstrFloat.td16 defm _F32 : I<(outs F32:$dst), (ins F32:$src), (outs), (ins),
17 [(set F32:$dst, (node F32:$src))],
27 defm _F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
28 [(set F32:$dst, (node F32:$lhs, F32:$rhs))],
37 defm _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins),
38 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
70 def : Pat<(fcopysign F64:$lhs, F32:$rhs),
71 (COPYSIGN_F64 F64:$lhs, (F64_PROMOTE_F32 F32:$rhs))>;
72 def : Pat<(fcopysign F32:$lhs, F64:$rhs),
73 (COPYSIGN_F32 F32:$lhs, (F32_DEMOTE_F64 F64:$rhs))>;
[all …]
DWebAssemblyRuntimeLibcallSignatures.cpp535 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
536 Params.push_back(wasm::ValType::F32); in getLibcallSignature()
539 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
543 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
547 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
551 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
556 Params.push_back(wasm::ValType::F32); in getLibcallSignature()
572 Params.push_back(wasm::ValType::F32); in getLibcallSignature()
584 Params.push_back(wasm::ValType::F32); in getLibcallSignature()
595 Rets.push_back(wasm::ValType::F32); in getLibcallSignature()
[all …]
DWebAssemblyFastISel.cpp1098 bool F32 = getSimpleType(FCmp->getOperand(0)->getType()) != MVT::f64; in selectFCmp() local
1103 Opc = F32 ? WebAssembly::EQ_F32 : WebAssembly::EQ_F64; in selectFCmp()
1106 Opc = F32 ? WebAssembly::NE_F32 : WebAssembly::NE_F64; in selectFCmp()
1109 Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64; in selectFCmp()
1112 Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64; in selectFCmp()
1115 Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64; in selectFCmp()
1118 Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64; in selectFCmp()
1121 Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64; in selectFCmp()
1125 Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64; in selectFCmp()
1129 Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64; in selectFCmp()
[all …]
DWebAssemblyInstrInfo.td277 defm "": ARGUMENT<F32, f32>;
359 defm "" : LOCAL<F32, global_op32>;
374 defm CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm),
376 [(set F32:$res, fpimm:$imm)],
DWebAssemblyRegisterInfo.td64 def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
DWebAssemblyInstrMemory.td60 defm LOAD_F32 : WebAssemblyLoad<F32, "f32.load", 0x2a, []>;
139 defm STORE_F32 : WebAssemblyStore<F32, "f32.store", 0x38>;
DWebAssemblyAsmPrinter.cpp116 case wasm::ValType::F32: in getInvokeSig()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonPatterns.td446 def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>;
459 def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>;
461 def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>;
464 def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>;
466 def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>;
470 def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>;
471 def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>;
704 def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>;
705 def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>;
706 def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>;
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/VE/
DVEInstrVec.td480 defm VBRDU : VBRDm<"vbrdu", 0x8c, V64, F32, VM>;
1000 let cx = 1, cx2 = 0 in defm PVANDUP : RVLm<"pvand.up", 0xc4, F32, V64, VM>;
1006 let cx = 1, cx2 = 0 in defm PVORUP : RVLm<"pvor.up", 0xc5, F32, V64, VM>;
1012 let cx = 1, cx2 = 0 in defm PVXORUP : RVLm<"pvxor.up", 0xc6, F32, V64, VM>;
1018 let cx = 1, cx2 = 0 in defm PVEQVUP : RVLm<"pveqv.up", 0xc7, F32, V64, VM>;
1052 let cx = 1, cx2 = 0 in defm PVSLLUP : RVSm<"pvsll.up", 0xe5, F32, V64, VM>;
1061 let cx = 1, cx2 = 0 in defm PVSRLUP : RVSm<"pvsrl.up", 0xf5, F32, V64, VM>;
1073 let cx = 1, cx2 = 0 in defm PVSLAUP : RVSm<"pvsla.up", 0xe6, F32, V64, VM>;
1089 let cx = 1, cx2 = 0 in defm PVSRAUP : RVSm<"pvsra.up", 0xf6, F32, V64, VM>;
1112 defm PVFADDUP : RVm<"pvfadd.up", 0xcc, V64, F32, VM, simm7fp>;
[all …]
DVEInstrInfo.td1044 defm LDU : LOADm<"ldu", 0x02, F32, f32, load>;
1102 defm STU : STOREm<"stu", 0x12, F32, f32, store>;
1129 defm DLDU : LOADm<"dldu", 0x0a, F32, f32, load>;
1321 defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32, cmov, simm7fp>;
1371 defm FADDS : RRFm<"fadd.s", 0x4C, F32, f32, fadd, simm7fp, mimmfp32>;
1376 defm FSUBS : RRFm<"fsub.s", 0x5C, F32, f32, fsub, simm7fp, mimmfp32>;
1381 defm FMULS : RRFm<"fmul.s", 0x4D, F32, f32, fmul, simm7fp, mimmfp32>;
1386 defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>;
1391 defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, cmpf, simm7fp, mimmfp32>;
1398 defm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32, fmaxnum, simm7fp, mimmfp32>;
[all …]
DVERegisterInfo.td181 def F32 : RegisterClass<"VE", [f32], 32,
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64SchedNeoverseN2.td1043 // ASIMD FP convert, long (F16 to F32)
1046 // ASIMD FP convert, long (F32 to F64)
1049 // ASIMD FP convert, narrow (F32 to F16)
1052 // ASIMD FP convert, narrow (F64 to F32)
1056 // ASIMD FP convert, other, D-form F32 and Q-form F64
1060 // ASIMD FP convert, other, D-form F16 and Q-form F32
1071 // ASIMD FP divide, D-form, F32
1077 // ASIMD FP divide, Q-form, F32
1083 // ASIMD FP max/min, reduce, F32 and D-form F16
1098 // ASIMD FP round, D-form F32 and Q-form F64
[all …]
DAArch64SchedA57.td467 // ASIMD FP divide, D-form, F32
469 // ASIMD FP divide, Q-form, F32
475 // ASIMD FP square root, D-form, F32
477 // ASIMD FP square root, Q-form, F32
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPULibCalls.cpp672 if ((getArgType(FInfo) == AMDGPULibFunc::F32 || in fold()
722 if (getArgType(FInfo) == AMDGPULibFunc::F32) { in TDOFold()
781 (CF1 && (getArgType(FInfo) == AMDGPULibFunc::F32))) in fold_divide()
901 double dval = (getArgType(FInfo) == AMDGPULibFunc::F32) in fold_pow()
964 double V = (getArgType(FInfo) == AMDGPULibFunc::F32) in fold_pow()
989 double V = (getArgType(FInfo) == AMDGPULibFunc::F32) in fold_pow()
996 if (getArgType(FInfo) == AMDGPULibFunc::F32) { in fold_pow()
1015 double y = (getArgType(FInfo) == AMDGPULibFunc::F32) in fold_pow()
1025 double y = (getArgType(FInfo) == AMDGPULibFunc::F32) in fold_pow()
1199 if (getArgType(FInfo) == AMDGPULibFunc::F32 && (getVecSize(FInfo) == 1) && in fold_sqrt()
[all …]
DSISchedule.td32 // Conversion to or from F32 (but not converting F64 to or from F32)
34 // F16 or F32 transcendental instructions (these are quarter rate)
DAMDGPULibFunc.cpp393 P.ArgType = AMDGPULibFunc::F32; P.VectorSize = 4; break; in getNextParam()
635 case 'f': res.ArgType = AMDGPULibFunc::F32; break; in parseItaniumParam()
742 case AMDGPULibFunc::F32: return "f"; in getItaniumTypeName()
893 case AMDGPULibFunc::F32: T = Type::getFloatTy(C); break; in getIntrinsicParamType()
DAMDGPULibFunc.h272 F32 = FLOAT | B32, enumerator
/openbsd/src/gnu/llvm/llvm/lib/Demangle/
DRustDemangle.cpp54 F32, enumerator
407 Type = BasicType::F32; in parseBasicType()
503 case BasicType::F32: in printBasicType()
/openbsd/src/gnu/llvm/llvm/include/llvm/Support/
DAMDGPUMetadata.h109 F32 = 8, enumerator
/openbsd/src/gnu/llvm/lld/wasm/
DWriterUtils.cpp27 case ValType::F32: in toString()
/openbsd/src/gnu/llvm/llvm/include/llvm/BinaryFormat/
DWasm.h427 F32 = WASM_TYPE_F32, enumerator
/openbsd/src/gnu/usr.bin/perl/lib/unicore/
DCJKRadicals.txt85 51; 2F32; 5E72
/openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td252 def D16 : SparcReg< 1, "F32">;
278 def Q8 : Rq< 1, "F32", [D16, D17]>;
/openbsd/src/gnu/llvm/llvm/lib/Support/
DAMDGPUMetadata.cpp85 YIO.enumCase(EN, "F32", ValueType::F32); in enumeration()

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