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Searched refs:Dest0 (Results 1 – 4 of 4) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCExpandAtomicPseudoInsts.cpp53 Register Dest0, Register Dest1, Register Src0, in PairedCopy() argument
57 if (Dest0 == Src1 && Dest1 == Src0) { in PairedCopy()
59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
62 } else if (Dest0 != Src0 || Dest1 != Src1) { in PairedCopy()
63 if (Dest0 == Src1 || Dest1 != Src0) { in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
67 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp1161 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair() local
1220 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeRead2Pair()
1349 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeImagePair() local
1353 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeImagePair()
1398 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSMemLoadImmPair() local
1402 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeSMemLoadImmPair()
1453 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair() local
1457 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeBufferLoadPair()
1512 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair() local
1516 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeTBufferLoadPair()
[all …]
DSIInstrInfo.cpp6389 MachineOperand &Dest0 = Inst.getOperand(0); in moveToVALU() local
6398 RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg())); in moveToVALU()
6410 MRI.replaceRegWith(Dest0.getReg(), DestReg); in moveToVALU()
DSIISelLowering.cpp4014 MachineOperand &Dest0 = MI.getOperand(0); in EmitInstrWithCustomInserter() local
4022 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1); in EmitInstrWithCustomInserter()