Searched refs:DesiredReg (Results 1 – 3 of 3) sorted by relevance
1733 Register DesiredReg = MI.getOperand(3).getReg(); in ExpandCMP_SWAP() local1741 assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) && in ExpandCMP_SWAP()1756 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg) in ExpandCMP_SWAP()1757 .addReg(DesiredReg, RegState::Kill); in ExpandCMP_SWAP()1778 .addReg(DesiredReg) in ExpandCMP_SWAP()1863 Register DesiredReg = MI.getOperand(3).getReg(); in ExpandCMP_SWAP_64() local1869 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); in ExpandCMP_SWAP_64()1870 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); in ExpandCMP_SWAP_64()
201 Register DesiredReg = MI.getOperand(3).getReg(); in expandCMP_SWAP() local225 .addReg(DesiredReg) in expandCMP_SWAP()
5027 const Register DesiredReg = constrainOperandRegClass( in selectAtomicCmpXchg() local5041 .addUse(DesiredReg) in selectAtomicCmpXchg()5047 .addUse(DesiredReg) in selectAtomicCmpXchg()