Searched refs:DKL_PLL_DIV0 (Results 1 – 2 of 2) sorted by relevance
57 #define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \ macro
3643 hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()3869 intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val, in dkl_pll_write()