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Searched refs:DDI_BUF_CTL (Results 1 – 9 of 9) sorted by relevance

/openbsd/src/sys/dev/pci/drm/i915/gvt/
Ddisplay.c223 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= in emulate_monitor_status_change()
226 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
286 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= in emulate_monitor_status_change()
288 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= in emulate_monitor_status_change()
316 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
318 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
347 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= in emulate_monitor_status_change()
349 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= in emulate_monitor_status_change()
429 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; in emulate_monitor_status_change()
430 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; in emulate_monitor_status_change()
[all …]
Dhandlers.c808 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
827 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); in fdi_auto_training_started()
2350 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2351 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2352 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2353 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2354 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
/openbsd/src/sys/dev/pci/drm/i915/display/
Dintel_ddi.c198 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_idle()
236 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), in intel_wait_ddi_buf_active()
787 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_get_encoder_pipes()
1483 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in hsw_set_signal_levels()
1484 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
2454 reg = DDI_BUF_CTL(port); in mtl_ddi_enable_d2d()
2931 reg = DDI_BUF_CTL(port); in mtl_ddi_disable_d2d_link()
2954 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in mtl_disable_ddi_buf()
2957 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); in mtl_disable_ddi_buf()
2981 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in disable_ddi_buf()
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Dintel_fdi.c935 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
939 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
982 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); in hsw_fdi_link_train()
983 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
1017 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); in hsw_fdi_disable()
Dicl_dsi.c514 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); in gen11_dsi_enable_ddi_buffer()
516 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in gen11_dsi_enable_ddi_buffer()
1364 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); in gen11_dsi_disable_port()
1366 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in gen11_dsi_disable_port()
Dintel_tc.c834 intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP, in adlp_tc_phy_take_ownership()
848 val = intel_de_read(i915, DDI_BUF_CTL(port)); in adlp_tc_phy_is_owned()
1462 return intel_de_read(i915, DDI_BUF_CTL(dig_port->base.port)) & in tc_port_is_enabled()
Dintel_display.c7775 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) in intel_ddi_crt_present()
/openbsd/src/sys/dev/pci/drm/i915/
Dintel_gvt_mmio_table.c521 MMIO_D(DDI_BUF_CTL(PORT_A)); in iterate_generic_mmio()
522 MMIO_D(DDI_BUF_CTL(PORT_B)); in iterate_generic_mmio()
523 MMIO_D(DDI_BUF_CTL(PORT_C)); in iterate_generic_mmio()
524 MMIO_D(DDI_BUF_CTL(PORT_D)); in iterate_generic_mmio()
525 MMIO_D(DDI_BUF_CTL(PORT_E)); in iterate_generic_mmio()
Di915_reg.h3857 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) macro