Searched refs:DC__VOLTAGE_STATES (Results 1 – 5 of 5) sorted by relevance
317 …double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML …536 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];537 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];599 double DCFCLKPerState[DC__VOLTAGE_STATES];600 double DCFCLKState[DC__VOLTAGE_STATES][2];601 double FabricClockPerState[DC__VOLTAGE_STATES];602 double SOCCLKPerState[DC__VOLTAGE_STATES];603 double PHYCLKPerState[DC__VOLTAGE_STATES];604 double DTBCLKPerState[DC__VOLTAGE_STATES];605 double MaxDppclk[DC__VOLTAGE_STATES];[all …]
39 #define DC__VOLTAGE_STATES 40 macro
182 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1460 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
6509 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } }; in UseMinimumDCFCLK()