| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 84 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
121 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
443 case ISD::CopyFromReg: in SUSchedulingCost()
548 case ISD::CopyFromReg: in initNumRegDefsLeft()
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| D | StatepointLowering.cpp | 349 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
1193 SDValue CopyFromReg = getCopyFromRegs(SI, RetTy); in visitGCResult() local
1195 assert(CopyFromReg.getNode()); in visitGCResult()
1196 setValue(&CI, CopyFromReg); in visitGCResult()
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| D | ScheduleDAGRRList.cpp | 325 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
714 case ISD::CopyFromReg: in EmitNode()
1282 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2288 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2389 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2460 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2477 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
3024 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
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| D | InstrEmitter.cpp | 350 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
1143 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
1228 case ISD::CopyFromReg: { in EmitSpecialNode()
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| D | ScheduleDAGSDNodes.cpp | 126 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
554 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
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| D | ScheduleDAGFast.cpp | 424 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
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| D | SelectionDAGDumper.cpp | 176 case ISD::CopyFromReg: return "CopyFromReg"; in getOperationName()
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| D | SelectionDAGBuilder.cpp | 5537 case ISD::CopyFromReg: { in getUnderlyingArgRegs()
9683 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) in visitPatchpoint()
10305 assert((Op.getOpcode() != ISD::CopyFromReg || in CopyValueToVirtualRegister()
10839 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { in LowerArguments()
10848 if (Res.getOpcode() == ISD::CopyFromReg) { in LowerArguments()
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| D | SelectionDAGISel.cpp | 2870 case ISD::CopyFromReg: in SelectCodeCommon()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AVR/ |
| D | AVRISelDAGToDAG.cpp | 246 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) { in SelectInlineAsmMemoryOperand()
297 SDValue CopyFromReg = in SelectInlineAsmMemoryOperand() local
300 OutOps.push_back(CopyFromReg); in SelectInlineAsmMemoryOperand()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | README-X86-64.txt | 46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
49 To get around this, isel emits a CopyFromReg from AX and then right shift it
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| D | X86InstrCompiler.td | 1484 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1487 // CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit
1492 N->getOpcode() != ISD::CopyFromReg &&
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| D | X86ISelDAGToDAG.cpp | 388 if (OtherOp->getOpcode() == ISD::CopyFromReg && in shouldAvoidImmediateInstFormsForSize()
2387 RHS.getNode()->getOpcode() == ISD::CopyFromReg || in matchAddressRecursively()
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| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | AArch64SME.rst | 256 ``CopyFromReg`` can only be **used after** the ``SMSTART/SMSTOP`` has been
259 We can use a CopyToReg -> CopyFromReg sequence for this, which moves the
272 t2: res,ch,glue = CopyFromReg t1, ...
275 t5: res,ch = CopyFromReg t4, Register:f64 %vreg
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 208 CopyFromReg, enumerator
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| D | SelectionDAG.h | 798 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
808 return getNode(ISD::CopyFromReg, dl, VTs,
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| /openbsd/src/gnu/llvm/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 388 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
394 N->getOpcode() != ISD::CopyFromReg;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 1429 if (Val.getOpcode() != ISD::CopyFromReg) in IsCopyFromSGPR()
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| D | SIISelLowering.cpp | 12751 assert(N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
12758 } while (N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
12766 case ISD::CopyFromReg: { in isSDNodeSourceOfDivergence()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 811 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1422 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1002 Opc != ISD::CopyFromReg && Opc != ISD::AssertSext && in SelectArithExtendedRegister()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 3666 if (Ptr.getOpcode() == ISD::CopyFromReg && in Select()
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| D | ARMISelLowering.cpp | 2939 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
15014 Copy->getOpcode() == ISD::CopyFromReg) { in PerformVMOVhrCombine()
15017 DCI.DAG.getNode(ISD::CopyFromReg, SDLoc(N), N->getValueType(0), Ops); in PerformVMOVhrCombine()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 4516 return AddrOp.getOpcode() == ISD::CopyFromReg; in isOffsetMultipleOf()
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