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Searched refs:CSR_WRITE_2 (Results 1 – 25 of 48) sorted by relevance

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/openbsd/src/sys/dev/isa/
Dif_ex.c142 #define CSR_WRITE_2(sc, off, value) \ macro
350 CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit); in ex_init()
352 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe); in ex_init()
353 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit); in ex_init()
425 CSR_WRITE_2(sc, MASK_REG, All_Int); in ex_start()
446 CSR_WRITE_2(sc, HOST_ADDR_REG, dest); in ex_start()
447 CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD); in ex_start()
448 CSR_WRITE_2(sc, IO_PORT_REG, 0); in ex_start()
449 CSR_WRITE_2(sc, IO_PORT_REG, next); in ex_start()
450 CSR_WRITE_2(sc, IO_PORT_REG, data_len); in ex_start()
[all …]
/openbsd/src/sys/dev/ic/
Dxl.c242 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
246 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
316 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); in xl_mii_readreg()
529 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
532 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
589 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT | rxfilt); in xl_iff_90x()
632 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); in xl_iff_905b()
639 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | in xl_iff_905b()
646 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT | rxfilt); in xl_iff_905b()
666 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); in xl_setcfg()
[all …]
Dfxp.c212 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
214 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); in fxp_eeprom_shiftin()
216 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
229 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); in fxp_eeprom_putword()
232 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword()
237 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); in fxp_eeprom_putword()
241 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword()
246 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); in fxp_eeprom_putword()
253 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_putword()
258 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); in fxp_eeprom_putword()
[all …]
Dan.c185 CSR_WRITE_2(sc, AN_INT_EN, 0); in an_attach()
186 CSR_WRITE_2(sc, AN_EVENT_ACK, 0xffff); in an_attach()
360 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); in an_rxeof()
370 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); in an_rxeof()
382 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); in an_rxeof()
392 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); in an_rxeof()
400 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); in an_rxeof()
412 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); in an_rxeof()
441 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); in an_rxeof()
493 CSR_WRITE_2(sc, AN_EVENT_ACK, status & (AN_EV_TX | AN_EV_TX_EXC)); in an_txeof()
[all …]
Dbwi.c655 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); in bwi_intr()
1017 CSR_WRITE_2(sc, data_reg, v); in bwi_memobj_write_2()
1030 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16); in bwi_memobj_write_4()
1033 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff); in bwi_memobj_write_4()
1077 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC); in bwi_mac_lateattach()
1152 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0); in bwi_mac_init()
1169 CSR_WRITE_2(sc, 0x60e, 0); in bwi_mac_init()
1170 CSR_WRITE_2(sc, 0x610, 0x8000); in bwi_mac_init()
1171 CSR_WRITE_2(sc, 0x604, 0); in bwi_mac_init()
1172 CSR_WRITE_2(sc, 0x606, 0x200); in bwi_mac_init()
[all …]
Dif_wi.c444 CSR_WRITE_2(sc, WI_INT_EN, mode); in wi_intr_enable()
451 CSR_WRITE_2(sc, WI_EVENT_ACK, mode); in wi_intr_ack()
466 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_intr()
467 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xffff); in wi_intr()
472 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_intr()
475 CSR_WRITE_2(sc, WI_EVENT_ACK, ~WI_INTRS); in wi_intr()
479 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); in wi_intr()
484 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_TX); in wi_intr()
490 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_ALLOC); in wi_intr()
497 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_INFO); in wi_intr()
[all …]
Drtl81x9.c318 CSR_WRITE_2(sc, RL_MII, 0); in rl_mii_readreg()
664 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); in rl_rxeof()
754 CSR_WRITE_2(sc, RL_IMR, 0x0000); in rl_intr()
762 CSR_WRITE_2(sc, RL_ISR, status); in rl_intr()
775 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_intr()
954 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_init()
1079 CSR_WRITE_2(sc, RL_IMR, 0x0000); in rl_stop()
1320 CSR_WRITE_2(sc, rl8139_reg, val); in rl_miibus_writereg()
Dacxvar.h86 #define CSR_WRITE_2(sc, reg, val) \ macro
94 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (b))
96 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & (~(b)))
Dre.c534 CSR_WRITE_2(sc, re8139_reg, data); in re_miibus_writereg()
1545 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr()
1553 CSR_WRITE_2(sc, RL_ISR, status); in re_intr()
1606 CSR_WRITE_2(sc, RL_IMR, sc->rl_intrs); in re_intr()
1913 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); in re_init()
1995 CSR_WRITE_2(sc, RL_ISR, sc->rl_intrs); in re_init()
2007 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); in re_init()
2009 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); in re_init()
2176 CSR_WRITE_2(sc, RL_IMR, 0x0000); in re_stop()
2177 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); in re_stop()
[all …]
Dbwivar.h81 #define CSR_WRITE_2(sc, reg, val) \ macro
87 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
92 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
97 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
Dacx.c1104 CSR_WRITE_2(sc, ACXREG_INTR_ACK, intr_status); in acx_intr()
1129 CSR_WRITE_2(sc, ACXREG_INTR_MASK, sc->chip_intr_disable); in acx_disable_intr()
1130 CSR_WRITE_2(sc, ACXREG_EVENT_MASK, 0); in acx_disable_intr()
1137 CSR_WRITE_2(sc, ACXREG_INTR_MASK, ~sc->chip_intr_enable); in acx_enable_intr()
1138 CSR_WRITE_2(sc, ACXREG_EVENT_MASK, ACXRV_EVENT_DISABLE); in acx_enable_intr()
1434 CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg | ACXRV_SOFT_RESET); in acx_reset()
1436 CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg); in acx_reset()
1542 CSR_WRITE_2(sc, ACXREG_ECPU_CTRL, ACXRV_ECPU_START); in acx_load_base_firmware()
1550 CSR_WRITE_2(sc, ACXREG_INTR_ACK, ACXRV_INTR_FCS_THRESH); in acx_load_base_firmware()
2285 CSR_WRITE_2(sc, ACXREG_INTR_TRIG, ACXRV_TRIG_TX_FINI); in acx_encap()
[all …]
Danvar.h49 #define CSR_WRITE_2(sc, reg, val) \ macro
Drtl81x9reg.h962 #define CSR_WRITE_2(sc, csr, val) \ macro
981 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
984 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/openbsd/src/sys/dev/pci/
Dif_vte.c119 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | in vte_miibus_readreg()
142 CSR_WRITE_2(sc, VTE_MMWD, val); in vte_miibus_writereg()
143 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | in vte_miibus_writereg()
197 CSR_WRITE_2(sc, VTE_MRICR, val); in vte_miibus_statchg()
206 CSR_WRITE_2(sc, VTE_MTICR, val); in vte_miibus_statchg()
695 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); in vte_start()
783 CSR_WRITE_2(sc, VTE_MCR0, mcr); in vte_mac_config()
857 CSR_WRITE_2(sc, VTE_MIER, 0); in vte_intr()
878 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); in vte_intr()
1059 CSR_WRITE_2(sc, VTE_MRDCR, prog | in vte_rxeof()
[all …]
Dif_ste.c119 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
122 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
207 CSR_WRITE_2(sc, STE_PHYCTL, 0); in ste_mii_readreg()
475 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); in ste_read_eeprom()
536 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); in ste_iff()
537 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); in ste_iff()
538 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); in ste_iff()
539 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); in ste_iff()
590 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); in ste_intr()
721 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); in ste_txeoc()
[all …]
Dif_stge.c779 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); in stge_intr()
1140 CSR_WRITE_2(sc, STGE_StationAddress0, in stge_init()
1142 CSR_WRITE_2(sc, STGE_StationAddress1, in stge_init()
1144 CSR_WRITE_2(sc, STGE_StationAddress2, in stge_init()
1188 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); in stge_init()
1195 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); in stge_init()
1216 CSR_WRITE_2(sc, STGE_IntStatus, 0xffff); in stge_init()
1217 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); in stge_init()
1231 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); in stge_init()
1232 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); in stge_init()
[all …]
Dif_vgevar.h101 #define CSR_WRITE_2(sc, reg, val) \ macro
116 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
123 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
Dif_tl.c294 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_read8()
301 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_read16()
308 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_read32()
315 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_write8()
322 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_write16()
323 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); in tl_dio_write16()
329 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_write32()
338 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_setbit()
349 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_clrbit()
360 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); in tl_dio_setbit16()
[all …]
Dif_vge.c352 CSR_WRITE_2(sc, VGE_MIIDATA, data); in vge_miibus_writereg()
1147 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); in vge_rxeof()
1465 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); in vge_start()
1550 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); in vge_init()
1554 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); in vge_init()
1555 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); in vge_init()
1562 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); in vge_init()
1571 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF); in vge_init()
1594 CSR_WRITE_2(sc, VGE_SSTIMER, 400); in vge_init()
1812 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); in vge_stop()
Dif_ipwreg.h294 #define CSR_WRITE_2(sc, reg, val) \ macro
314 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
Dif_wi_pci.c409 CSR_WRITE_2(sc, WI_SW0, WI_DRVR_MAGIC); in wi_pci_plx_attach()
526 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_pci_common_attach()
527 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); in wi_pci_common_attach()
Dif_vr.c186 CSR_WRITE_2(sc, reg, \
190 CSR_WRITE_2(sc, reg, \
256 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); in vr_mii_writereg()
1098 CSR_WRITE_2(sc, VR_ISR, status); in vr_intr()
1454 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| in vr_init()
1464 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); in vr_init()
1465 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); in vr_init()
1617 CSR_WRITE_2(sc, VR_IMR, 0x0000); in vr_stop()
Dif_iwireg.h473 #define CSR_WRITE_2(sc, reg, val) \ macro
492 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/openbsd/src/sys/arch/macppc/dev/
Dif_wi_obio.c124 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_obio_attach()
125 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xffff); in wi_obio_attach()
/openbsd/src/sys/dev/pcmcia/
Dif_wi_pcmcia.c411 CSR_WRITE_2(sc, WI_INT_EN, 0); in wi_pcmcia_attach()
412 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xffff); in wi_pcmcia_attach()

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