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Searched refs:CSR_READ_1 (Results 1 – 25 of 32) sorted by relevance

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/openbsd/src/sys/dev/isa/
Dif_ex.c132 #define CSR_READ_1(sc, off) \ macro
157 if (((count1 = CSR_READ_1(sc, ID_REG)) & Id_Mask) != Id_Sig) in ex_look_for_card()
159 count2 = CSR_READ_1(sc, ID_REG); in ex_look_for_card()
160 count2 = CSR_READ_1(sc, ID_REG); in ex_look_for_card()
161 count2 = CSR_READ_1(sc, ID_REG); in ex_look_for_card()
302 temp_reg = CSR_READ_1(sc, EEPROM_REG); in ex_init()
314 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | in ex_init()
316 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | in ex_init()
318 CSR_WRITE_1(sc, REG3, (CSR_READ_1(sc, REG3) & 0x3f)); in ex_init()
320 CSR_WRITE_1(sc, INT_NO_REG, (CSR_READ_1(sc, INT_NO_REG) & 0xf8) | in ex_init()
[all …]
/openbsd/src/sys/dev/pci/
Dif_vgevar.h110 #define CSR_READ_1(sc, reg) \ macro
114 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
121 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
Dif_vge.c198 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) in vge_eeprom_getword()
240 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); in vge_read_eeprom()
253 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_stop()
273 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) in vge_miipoll_start()
290 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) in vge_miipoll_start()
305 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) in vge_miibus_readreg()
321 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) in vge_miibus_readreg()
342 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) in vge_miibus_writereg()
360 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) in vge_miibus_writereg()
427 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) in vge_cam_set()
[all …]
Dif_vr.c179 CSR_READ_1(sc, reg) | (x))
183 CSR_READ_1(sc, reg) & ~(x))
203 CSR_READ_1(sc, VR_MIICMD) | (x))
207 CSR_READ_1(sc, VR_MIICMD) & ~(x))
220 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| in vr_mii_readreg()
228 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) in vr_mii_readreg()
251 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| in vr_mii_writereg()
261 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) in vr_mii_writereg()
338 rxfilt = CSR_READ_1(sc, VR_RXCFG); in vr_iff()
591 sc->arpcom.ac_enaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); in vr_attach()
Dif_ste.c125 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
128 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
500 rxmode = CSR_READ_1(sc, STE_RX_MODE); in ste_iff()
703 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & in ste_txeoc()
772 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) in ste_stats_update()
773 + CSR_READ_1(sc, STE_MULTI_COLLS) in ste_stats_update()
774 + CSR_READ_1(sc, STE_SINGLE_COLLS); in ste_stats_update()
Dif_re_pci.c193 cfg = CSR_READ_1(sc, RL_CFG2); in re_pci_attach()
Dif_ipwreg.h282 #define CSR_READ_1(sc, reg) \ macro
Dif_wbreg.h396 #define CSR_READ_1(sc, reg) \ macro
Dif_lge.c604 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) in lge_list_rx_init()
771 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); in lge_txeof()
949 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) in lge_start()
Dif_stereg.h457 #define CSR_READ_1(sc, reg) \ macro
Dif_vrreg.h554 #define CSR_READ_1(sc, reg) \ macro
Dif_lgereg.h542 #define CSR_READ_1(sc, reg) \ macro
Dif_tlreg.h511 #define CSR_READ_1(sc, reg) \ macro
Dif_stgereg.h58 #define CSR_READ_1(_sc, reg) \ macro
Dif_iwireg.h457 #define CSR_READ_1(sc, reg) \ macro
Dif_tl.c295 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); in tl_dio_read8()
339 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); in tl_dio_setbit()
350 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); in tl_dio_clrbit()
Dif_stge.c331 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & in stge_attach()
1579 return (CSR_READ_1(sc, STGE_PhyCtrl)); in stge_mii_bitbang_read()
/openbsd/src/sys/dev/ic/
Dre.c213 CSR_READ_1(sc, RL_EECMD) | x)
217 CSR_READ_1(sc, RL_EECMD) & ~x)
329 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) in re_eeprom_getword()
375 rval = CSR_READ_1(sc, RL_GMEDIASTAT); in re_gmii_readreg()
469 rval = CSR_READ_1(sc, RL_MEDIASTAT); in re_miibus_readreg()
646 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) in re_reset()
836 cfg2 = CSR_READ_1(sc, sc->rl_cfg2); in re_attach()
863 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); in re_attach()
1052 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); in re_attach()
1054 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); in re_attach()
[all …]
Drtl81x9.c155 CSR_READ_1(sc, RL_EECMD) | x)
159 CSR_READ_1(sc, RL_EECMD) & ~x)
214 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) in rl_eeprom_getword()
254 CSR_READ_1(sc, RL_MII) | x)
258 CSR_READ_1(sc, RL_MII) & ~x)
499 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) in rl_reset()
579 while ((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { in rl_rxeof()
1271 return (CSR_READ_1(sc, RL_MEDIASTAT)); in rl_miibus_readreg()
Dxl.c477 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); in xl_miibus_statchg()
570 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_iff_90x()
609 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); in xl_iff_905b()
744 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); in xl_setmode()
1352 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { in xl_txeoc()
1492 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); in xl_stats_update()
1507 CSR_READ_1(sc, XL_W4_BADSSD); in xl_stats_update()
1987 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); in xl_init()
2108 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
2117 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) in xl_ifmedia_sts()
Drtl81x9reg.h971 #define CSR_READ_1(sc, csr) \ macro
975 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
978 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
Dmtd8xxreg.h200 #define CSR_READ_1(reg) bus_space_read_1(sc->sc_bust, sc->sc_bush, reg) macro
Dif_wireg.h100 #define CSR_READ_1(sc, reg) \ macro
Dacxvar.h76 #define CSR_READ_1(sc, reg) \ macro
Dxlreg.h654 #define CSR_READ_1(sc, reg) \ macro

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