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Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK (Results 1 – 13 of 13) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h1875 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000 macro
Dgfx_8_1_sh_mask.h2397 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000 macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11207 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_9_4_3_sh_mask.h14300 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_9_1_sh_mask.h12684 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_9_2_1_sh_mask.h12482 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_9_4_2_sh_mask.h2591 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_11_5_0_sh_mask.h12357 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_11_0_0_sh_mask.h15619 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_12_0_0_sh_mask.h12001 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_11_0_3_sh_mask.h17774 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_10_1_0_sh_mask.h18166 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro
Dgc_10_3_0_sh_mask.h16517 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK … macro