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Searched refs:CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK (Results 1 – 16 of 16) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v7_0.c3059 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | in gfx_v7_0_enable_gui_idle_interrupt()
3062 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | in gfx_v7_0_enable_gui_idle_interrupt()
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h2362 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L macro
Dgfx_7_2_sh_mask.h1175 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 macro
Dgfx_8_0_sh_mask.h1501 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 macro
Dgfx_8_1_sh_mask.h2025 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h11006 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_9_4_3_sh_mask.h14012 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_9_1_sh_mask.h12483 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_9_2_1_sh_mask.h12287 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_9_4_2_sh_mask.h2303 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_11_5_0_sh_mask.h12232 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_11_0_0_sh_mask.h15416 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_12_0_0_sh_mask.h11852 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_11_0_3_sh_mask.h17571 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_10_1_0_sh_mask.h17947 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro
Dgc_10_3_0_sh_mask.h16211 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK … macro