1 /*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27
28 #include <linux/pci.h>
29
30 #include <drm/drm_device.h>
31 #include <drm/drm_edid.h>
32 #include <drm/radeon_drm.h>
33
34 #include "radeon.h"
35 #include "radeon_legacy_encoders.h"
36 #include "atom.h"
37
38 #if defined(CONFIG_PPC_PMAC) && defined(__linux__)
39 /* not sure which of these are needed */
40 #include <asm/machdep.h>
41 #include <asm/pmac_feature.h>
42 #include <asm/prom.h>
43 #elif defined(CONFIG_PPC_PMAC)
44 #include <linux/of.h>
45 #endif /* CONFIG_PPC_PMAC */
46
47 /* old legacy ATI BIOS routines */
48
49 /* COMBIOS table offsets */
50 enum radeon_combios_table_offset {
51 /* absolute offset tables */
52 COMBIOS_ASIC_INIT_1_TABLE,
53 COMBIOS_BIOS_SUPPORT_TABLE,
54 COMBIOS_DAC_PROGRAMMING_TABLE,
55 COMBIOS_MAX_COLOR_DEPTH_TABLE,
56 COMBIOS_CRTC_INFO_TABLE,
57 COMBIOS_PLL_INFO_TABLE,
58 COMBIOS_TV_INFO_TABLE,
59 COMBIOS_DFP_INFO_TABLE,
60 COMBIOS_HW_CONFIG_INFO_TABLE,
61 COMBIOS_MULTIMEDIA_INFO_TABLE,
62 COMBIOS_TV_STD_PATCH_TABLE,
63 COMBIOS_LCD_INFO_TABLE,
64 COMBIOS_MOBILE_INFO_TABLE,
65 COMBIOS_PLL_INIT_TABLE,
66 COMBIOS_MEM_CONFIG_TABLE,
67 COMBIOS_SAVE_MASK_TABLE,
68 COMBIOS_HARDCODED_EDID_TABLE,
69 COMBIOS_ASIC_INIT_2_TABLE,
70 COMBIOS_CONNECTOR_INFO_TABLE,
71 COMBIOS_DYN_CLK_1_TABLE,
72 COMBIOS_RESERVED_MEM_TABLE,
73 COMBIOS_EXT_TMDS_INFO_TABLE,
74 COMBIOS_MEM_CLK_INFO_TABLE,
75 COMBIOS_EXT_DAC_INFO_TABLE,
76 COMBIOS_MISC_INFO_TABLE,
77 COMBIOS_CRT_INFO_TABLE,
78 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
79 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
80 COMBIOS_FAN_SPEED_INFO_TABLE,
81 COMBIOS_OVERDRIVE_INFO_TABLE,
82 COMBIOS_OEM_INFO_TABLE,
83 COMBIOS_DYN_CLK_2_TABLE,
84 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
85 COMBIOS_I2C_INFO_TABLE,
86 /* relative offset tables */
87 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
88 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
89 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
90 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
91 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
92 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
93 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
94 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
95 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
96 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
97 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
98 };
99
100 enum radeon_combios_ddc {
101 DDC_NONE_DETECTED,
102 DDC_MONID,
103 DDC_DVI,
104 DDC_VGA,
105 DDC_CRT2,
106 DDC_LCD,
107 DDC_GPIO,
108 };
109
110 enum radeon_combios_connector {
111 CONNECTOR_NONE_LEGACY,
112 CONNECTOR_PROPRIETARY_LEGACY,
113 CONNECTOR_CRT_LEGACY,
114 CONNECTOR_DVI_I_LEGACY,
115 CONNECTOR_DVI_D_LEGACY,
116 CONNECTOR_CTV_LEGACY,
117 CONNECTOR_STV_LEGACY,
118 CONNECTOR_UNSUPPORTED_LEGACY
119 };
120
121 static const int legacy_connector_convert[] = {
122 DRM_MODE_CONNECTOR_Unknown,
123 DRM_MODE_CONNECTOR_DVID,
124 DRM_MODE_CONNECTOR_VGA,
125 DRM_MODE_CONNECTOR_DVII,
126 DRM_MODE_CONNECTOR_DVID,
127 DRM_MODE_CONNECTOR_Composite,
128 DRM_MODE_CONNECTOR_SVIDEO,
129 DRM_MODE_CONNECTOR_Unknown,
130 };
131
combios_get_table_offset(struct drm_device * dev,enum radeon_combios_table_offset table)132 static uint16_t combios_get_table_offset(struct drm_device *dev,
133 enum radeon_combios_table_offset table)
134 {
135 struct radeon_device *rdev = dev->dev_private;
136 int rev, size;
137 uint16_t offset = 0, check_offset;
138
139 if (!rdev->bios)
140 return 0;
141
142 switch (table) {
143 /* absolute offset tables */
144 case COMBIOS_ASIC_INIT_1_TABLE:
145 check_offset = 0xc;
146 break;
147 case COMBIOS_BIOS_SUPPORT_TABLE:
148 check_offset = 0x14;
149 break;
150 case COMBIOS_DAC_PROGRAMMING_TABLE:
151 check_offset = 0x2a;
152 break;
153 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
154 check_offset = 0x2c;
155 break;
156 case COMBIOS_CRTC_INFO_TABLE:
157 check_offset = 0x2e;
158 break;
159 case COMBIOS_PLL_INFO_TABLE:
160 check_offset = 0x30;
161 break;
162 case COMBIOS_TV_INFO_TABLE:
163 check_offset = 0x32;
164 break;
165 case COMBIOS_DFP_INFO_TABLE:
166 check_offset = 0x34;
167 break;
168 case COMBIOS_HW_CONFIG_INFO_TABLE:
169 check_offset = 0x36;
170 break;
171 case COMBIOS_MULTIMEDIA_INFO_TABLE:
172 check_offset = 0x38;
173 break;
174 case COMBIOS_TV_STD_PATCH_TABLE:
175 check_offset = 0x3e;
176 break;
177 case COMBIOS_LCD_INFO_TABLE:
178 check_offset = 0x40;
179 break;
180 case COMBIOS_MOBILE_INFO_TABLE:
181 check_offset = 0x42;
182 break;
183 case COMBIOS_PLL_INIT_TABLE:
184 check_offset = 0x46;
185 break;
186 case COMBIOS_MEM_CONFIG_TABLE:
187 check_offset = 0x48;
188 break;
189 case COMBIOS_SAVE_MASK_TABLE:
190 check_offset = 0x4a;
191 break;
192 case COMBIOS_HARDCODED_EDID_TABLE:
193 check_offset = 0x4c;
194 break;
195 case COMBIOS_ASIC_INIT_2_TABLE:
196 check_offset = 0x4e;
197 break;
198 case COMBIOS_CONNECTOR_INFO_TABLE:
199 check_offset = 0x50;
200 break;
201 case COMBIOS_DYN_CLK_1_TABLE:
202 check_offset = 0x52;
203 break;
204 case COMBIOS_RESERVED_MEM_TABLE:
205 check_offset = 0x54;
206 break;
207 case COMBIOS_EXT_TMDS_INFO_TABLE:
208 check_offset = 0x58;
209 break;
210 case COMBIOS_MEM_CLK_INFO_TABLE:
211 check_offset = 0x5a;
212 break;
213 case COMBIOS_EXT_DAC_INFO_TABLE:
214 check_offset = 0x5c;
215 break;
216 case COMBIOS_MISC_INFO_TABLE:
217 check_offset = 0x5e;
218 break;
219 case COMBIOS_CRT_INFO_TABLE:
220 check_offset = 0x60;
221 break;
222 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
223 check_offset = 0x62;
224 break;
225 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
226 check_offset = 0x64;
227 break;
228 case COMBIOS_FAN_SPEED_INFO_TABLE:
229 check_offset = 0x66;
230 break;
231 case COMBIOS_OVERDRIVE_INFO_TABLE:
232 check_offset = 0x68;
233 break;
234 case COMBIOS_OEM_INFO_TABLE:
235 check_offset = 0x6a;
236 break;
237 case COMBIOS_DYN_CLK_2_TABLE:
238 check_offset = 0x6c;
239 break;
240 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
241 check_offset = 0x6e;
242 break;
243 case COMBIOS_I2C_INFO_TABLE:
244 check_offset = 0x70;
245 break;
246 /* relative offset tables */
247 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
248 check_offset =
249 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
250 if (check_offset) {
251 rev = RBIOS8(check_offset);
252 if (rev > 0) {
253 check_offset = RBIOS16(check_offset + 0x3);
254 if (check_offset)
255 offset = check_offset;
256 }
257 }
258 break;
259 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
260 check_offset =
261 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
262 if (check_offset) {
263 rev = RBIOS8(check_offset);
264 if (rev > 0) {
265 check_offset = RBIOS16(check_offset + 0x5);
266 if (check_offset)
267 offset = check_offset;
268 }
269 }
270 break;
271 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
272 check_offset =
273 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
274 if (check_offset) {
275 rev = RBIOS8(check_offset);
276 if (rev > 0) {
277 check_offset = RBIOS16(check_offset + 0x7);
278 if (check_offset)
279 offset = check_offset;
280 }
281 }
282 break;
283 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
284 check_offset =
285 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
286 if (check_offset) {
287 rev = RBIOS8(check_offset);
288 if (rev == 2) {
289 check_offset = RBIOS16(check_offset + 0x9);
290 if (check_offset)
291 offset = check_offset;
292 }
293 }
294 break;
295 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
296 check_offset =
297 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
298 if (check_offset) {
299 while (RBIOS8(check_offset++));
300 check_offset += 2;
301 if (check_offset)
302 offset = check_offset;
303 }
304 break;
305 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
306 check_offset =
307 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
308 if (check_offset) {
309 check_offset = RBIOS16(check_offset + 0x11);
310 if (check_offset)
311 offset = check_offset;
312 }
313 break;
314 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
315 check_offset =
316 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
317 if (check_offset) {
318 check_offset = RBIOS16(check_offset + 0x13);
319 if (check_offset)
320 offset = check_offset;
321 }
322 break;
323 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
324 check_offset =
325 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
326 if (check_offset) {
327 check_offset = RBIOS16(check_offset + 0x15);
328 if (check_offset)
329 offset = check_offset;
330 }
331 break;
332 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
333 check_offset =
334 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
335 if (check_offset) {
336 check_offset = RBIOS16(check_offset + 0x17);
337 if (check_offset)
338 offset = check_offset;
339 }
340 break;
341 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
344 if (check_offset) {
345 check_offset = RBIOS16(check_offset + 0x2);
346 if (check_offset)
347 offset = check_offset;
348 }
349 break;
350 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
351 check_offset =
352 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
353 if (check_offset) {
354 check_offset = RBIOS16(check_offset + 0x4);
355 if (check_offset)
356 offset = check_offset;
357 }
358 break;
359 default:
360 check_offset = 0;
361 break;
362 }
363
364 size = RBIOS8(rdev->bios_header_start + 0x6);
365 /* check absolute offset tables */
366 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
367 offset = RBIOS16(rdev->bios_header_start + check_offset);
368
369 return offset;
370 }
371
radeon_combios_check_hardcoded_edid(struct radeon_device * rdev)372 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
373 {
374 int edid_info, size;
375 const struct drm_edid *edid;
376 unsigned char *raw;
377 edid_info = combios_get_table_offset(rdev_to_drm(rdev), COMBIOS_HARDCODED_EDID_TABLE);
378 if (!edid_info)
379 return false;
380
381 raw = rdev->bios + edid_info;
382 size = EDID_LENGTH * (raw[0x7e] + 1);
383 edid = drm_edid_alloc(raw, size);
384
385 if (!drm_edid_valid(edid)) {
386 drm_edid_free(edid);
387 return false;
388 }
389
390 rdev->mode_info.bios_hardcoded_edid = edid;
391 return true;
392 }
393
394 /* this is used for atom LCDs as well */
395 struct edid *
radeon_bios_get_hardcoded_edid(struct radeon_device * rdev)396 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
397 {
398 return drm_edid_duplicate(drm_edid_raw(rdev->mode_info.bios_hardcoded_edid));
399 }
400
401 #ifdef __clang__
combios_setup_i2c_bus(struct radeon_device * rdev,enum radeon_combios_ddc ddc,u32 clk_mask,u32 data_mask)402 static inline struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
403 enum radeon_combios_ddc ddc,
404 u32 clk_mask,
405 u32 data_mask)
406 #else
407 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
408 enum radeon_combios_ddc ddc,
409 u32 clk_mask,
410 u32 data_mask)
411 #endif
412 {
413 struct radeon_i2c_bus_rec i2c;
414 int ddc_line = 0;
415
416 /* ddc id = mask reg
417 * DDC_NONE_DETECTED = none
418 * DDC_DVI = RADEON_GPIO_DVI_DDC
419 * DDC_VGA = RADEON_GPIO_VGA_DDC
420 * DDC_LCD = RADEON_GPIOPAD_MASK
421 * DDC_GPIO = RADEON_MDGPIO_MASK
422 * r1xx
423 * DDC_MONID = RADEON_GPIO_MONID
424 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
425 * r200
426 * DDC_MONID = RADEON_GPIO_MONID
427 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
428 * r300/r350
429 * DDC_MONID = RADEON_GPIO_DVI_DDC
430 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
431 * rv2xx/rv3xx
432 * DDC_MONID = RADEON_GPIO_MONID
433 * DDC_CRT2 = RADEON_GPIO_MONID
434 * rs3xx/rs4xx
435 * DDC_MONID = RADEON_GPIOPAD_MASK
436 * DDC_CRT2 = RADEON_GPIO_MONID
437 */
438 switch (ddc) {
439 case DDC_NONE_DETECTED:
440 default:
441 ddc_line = 0;
442 break;
443 case DDC_DVI:
444 ddc_line = RADEON_GPIO_DVI_DDC;
445 break;
446 case DDC_VGA:
447 ddc_line = RADEON_GPIO_VGA_DDC;
448 break;
449 case DDC_LCD:
450 ddc_line = RADEON_GPIOPAD_MASK;
451 break;
452 case DDC_GPIO:
453 ddc_line = RADEON_MDGPIO_MASK;
454 break;
455 case DDC_MONID:
456 if (rdev->family == CHIP_RS300 ||
457 rdev->family == CHIP_RS400 ||
458 rdev->family == CHIP_RS480)
459 ddc_line = RADEON_GPIOPAD_MASK;
460 else if (rdev->family == CHIP_R300 ||
461 rdev->family == CHIP_R350) {
462 ddc_line = RADEON_GPIO_DVI_DDC;
463 ddc = DDC_DVI;
464 } else
465 ddc_line = RADEON_GPIO_MONID;
466 break;
467 case DDC_CRT2:
468 if (rdev->family == CHIP_R200 ||
469 rdev->family == CHIP_R300 ||
470 rdev->family == CHIP_R350) {
471 ddc_line = RADEON_GPIO_DVI_DDC;
472 ddc = DDC_DVI;
473 } else if (rdev->family == CHIP_RS300 ||
474 rdev->family == CHIP_RS400 ||
475 rdev->family == CHIP_RS480)
476 ddc_line = RADEON_GPIO_MONID;
477 else if (rdev->family >= CHIP_RV350) {
478 ddc_line = RADEON_GPIO_MONID;
479 ddc = DDC_MONID;
480 } else
481 ddc_line = RADEON_GPIO_CRT2_DDC;
482 break;
483 }
484
485 if (ddc_line == RADEON_GPIOPAD_MASK) {
486 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
487 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
488 i2c.a_clk_reg = RADEON_GPIOPAD_A;
489 i2c.a_data_reg = RADEON_GPIOPAD_A;
490 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
491 i2c.en_data_reg = RADEON_GPIOPAD_EN;
492 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
493 i2c.y_data_reg = RADEON_GPIOPAD_Y;
494 } else if (ddc_line == RADEON_MDGPIO_MASK) {
495 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
496 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
497 i2c.a_clk_reg = RADEON_MDGPIO_A;
498 i2c.a_data_reg = RADEON_MDGPIO_A;
499 i2c.en_clk_reg = RADEON_MDGPIO_EN;
500 i2c.en_data_reg = RADEON_MDGPIO_EN;
501 i2c.y_clk_reg = RADEON_MDGPIO_Y;
502 i2c.y_data_reg = RADEON_MDGPIO_Y;
503 } else {
504 i2c.mask_clk_reg = ddc_line;
505 i2c.mask_data_reg = ddc_line;
506 i2c.a_clk_reg = ddc_line;
507 i2c.a_data_reg = ddc_line;
508 i2c.en_clk_reg = ddc_line;
509 i2c.en_data_reg = ddc_line;
510 i2c.y_clk_reg = ddc_line;
511 i2c.y_data_reg = ddc_line;
512 }
513
514 if (clk_mask && data_mask) {
515 /* system specific masks */
516 i2c.mask_clk_mask = clk_mask;
517 i2c.mask_data_mask = data_mask;
518 i2c.a_clk_mask = clk_mask;
519 i2c.a_data_mask = data_mask;
520 i2c.en_clk_mask = clk_mask;
521 i2c.en_data_mask = data_mask;
522 i2c.y_clk_mask = clk_mask;
523 i2c.y_data_mask = data_mask;
524 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
525 (ddc_line == RADEON_MDGPIO_MASK)) {
526 /* default gpiopad masks */
527 i2c.mask_clk_mask = (0x20 << 8);
528 i2c.mask_data_mask = 0x80;
529 i2c.a_clk_mask = (0x20 << 8);
530 i2c.a_data_mask = 0x80;
531 i2c.en_clk_mask = (0x20 << 8);
532 i2c.en_data_mask = 0x80;
533 i2c.y_clk_mask = (0x20 << 8);
534 i2c.y_data_mask = 0x80;
535 } else {
536 /* default masks for ddc pads */
537 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
538 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
539 i2c.a_clk_mask = RADEON_GPIO_A_1;
540 i2c.a_data_mask = RADEON_GPIO_A_0;
541 i2c.en_clk_mask = RADEON_GPIO_EN_1;
542 i2c.en_data_mask = RADEON_GPIO_EN_0;
543 i2c.y_clk_mask = RADEON_GPIO_Y_1;
544 i2c.y_data_mask = RADEON_GPIO_Y_0;
545 }
546
547 switch (rdev->family) {
548 case CHIP_R100:
549 case CHIP_RV100:
550 case CHIP_RS100:
551 case CHIP_RV200:
552 case CHIP_RS200:
553 case CHIP_RS300:
554 switch (ddc_line) {
555 case RADEON_GPIO_DVI_DDC:
556 i2c.hw_capable = true;
557 break;
558 default:
559 i2c.hw_capable = false;
560 break;
561 }
562 break;
563 case CHIP_R200:
564 switch (ddc_line) {
565 case RADEON_GPIO_DVI_DDC:
566 case RADEON_GPIO_MONID:
567 i2c.hw_capable = true;
568 break;
569 default:
570 i2c.hw_capable = false;
571 break;
572 }
573 break;
574 case CHIP_RV250:
575 case CHIP_RV280:
576 switch (ddc_line) {
577 case RADEON_GPIO_VGA_DDC:
578 case RADEON_GPIO_DVI_DDC:
579 case RADEON_GPIO_CRT2_DDC:
580 i2c.hw_capable = true;
581 break;
582 default:
583 i2c.hw_capable = false;
584 break;
585 }
586 break;
587 case CHIP_R300:
588 case CHIP_R350:
589 switch (ddc_line) {
590 case RADEON_GPIO_VGA_DDC:
591 case RADEON_GPIO_DVI_DDC:
592 i2c.hw_capable = true;
593 break;
594 default:
595 i2c.hw_capable = false;
596 break;
597 }
598 break;
599 case CHIP_RV350:
600 case CHIP_RV380:
601 case CHIP_RS400:
602 case CHIP_RS480:
603 switch (ddc_line) {
604 case RADEON_GPIO_VGA_DDC:
605 case RADEON_GPIO_DVI_DDC:
606 i2c.hw_capable = true;
607 break;
608 case RADEON_GPIO_MONID:
609 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
610 * reliably on some pre-r4xx hardware; not sure why.
611 */
612 i2c.hw_capable = false;
613 break;
614 default:
615 i2c.hw_capable = false;
616 break;
617 }
618 break;
619 default:
620 i2c.hw_capable = false;
621 break;
622 }
623 i2c.mm_i2c = false;
624
625 i2c.i2c_id = ddc;
626 i2c.hpd = RADEON_HPD_NONE;
627
628 if (ddc_line)
629 i2c.valid = true;
630 else
631 i2c.valid = false;
632
633 return i2c;
634 }
635
radeon_combios_get_i2c_info_from_table(struct radeon_device * rdev)636 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
637 {
638 struct drm_device *dev = rdev_to_drm(rdev);
639 struct radeon_i2c_bus_rec i2c;
640 u16 offset;
641 u8 id, blocks, clk, data;
642 int i;
643
644 i2c.valid = false;
645
646 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
647 if (offset) {
648 blocks = RBIOS8(offset + 2);
649 for (i = 0; i < blocks; i++) {
650 id = RBIOS8(offset + 3 + (i * 5) + 0);
651 if (id == 136) {
652 clk = RBIOS8(offset + 3 + (i * 5) + 3);
653 data = RBIOS8(offset + 3 + (i * 5) + 4);
654 /* gpiopad */
655 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
656 (1 << clk), (1 << data));
657 break;
658 }
659 }
660 }
661 return i2c;
662 }
663
radeon_combios_i2c_init(struct radeon_device * rdev)664 void radeon_combios_i2c_init(struct radeon_device *rdev)
665 {
666 struct drm_device *dev = rdev_to_drm(rdev);
667 struct radeon_i2c_bus_rec i2c;
668
669 /* actual hw pads
670 * r1xx/rs2xx/rs3xx
671 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
672 * r200
673 * 0x60, 0x64, 0x68, mm
674 * r300/r350
675 * 0x60, 0x64, mm
676 * rv2xx/rv3xx/rs4xx
677 * 0x60, 0x64, 0x68, gpiopads, mm
678 */
679
680 /* 0x60 */
681 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
682 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
683 /* 0x64 */
684 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
685 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
686
687 /* mm i2c */
688 i2c.valid = true;
689 i2c.hw_capable = true;
690 i2c.mm_i2c = true;
691 i2c.i2c_id = 0xa0;
692 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
693
694 if (rdev->family == CHIP_R300 ||
695 rdev->family == CHIP_R350) {
696 /* only 2 sw i2c pads */
697 } else if (rdev->family == CHIP_RS300 ||
698 rdev->family == CHIP_RS400 ||
699 rdev->family == CHIP_RS480) {
700 /* 0x68 */
701 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
702 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
703
704 /* gpiopad */
705 i2c = radeon_combios_get_i2c_info_from_table(rdev);
706 if (i2c.valid)
707 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
708 } else if ((rdev->family == CHIP_R200) ||
709 (rdev->family >= CHIP_R300)) {
710 /* 0x68 */
711 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
712 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
713 } else {
714 /* 0x68 */
715 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
716 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
717 /* 0x6c */
718 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
719 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
720 }
721 }
722
radeon_combios_get_clock_info(struct drm_device * dev)723 bool radeon_combios_get_clock_info(struct drm_device *dev)
724 {
725 struct radeon_device *rdev = dev->dev_private;
726 uint16_t pll_info;
727 struct radeon_pll *p1pll = &rdev->clock.p1pll;
728 struct radeon_pll *p2pll = &rdev->clock.p2pll;
729 struct radeon_pll *spll = &rdev->clock.spll;
730 struct radeon_pll *mpll = &rdev->clock.mpll;
731 int8_t rev;
732 uint16_t sclk, mclk;
733
734 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
735 if (pll_info) {
736 rev = RBIOS8(pll_info);
737
738 /* pixel clocks */
739 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
740 p1pll->reference_div = RBIOS16(pll_info + 0x10);
741 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
742 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
743 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
744 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
745
746 if (rev > 9) {
747 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
748 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
749 } else {
750 p1pll->pll_in_min = 40;
751 p1pll->pll_in_max = 500;
752 }
753 *p2pll = *p1pll;
754
755 /* system clock */
756 spll->reference_freq = RBIOS16(pll_info + 0x1a);
757 spll->reference_div = RBIOS16(pll_info + 0x1c);
758 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
759 spll->pll_out_max = RBIOS32(pll_info + 0x22);
760
761 if (rev > 10) {
762 spll->pll_in_min = RBIOS32(pll_info + 0x48);
763 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
764 } else {
765 /* ??? */
766 spll->pll_in_min = 40;
767 spll->pll_in_max = 500;
768 }
769
770 /* memory clock */
771 mpll->reference_freq = RBIOS16(pll_info + 0x26);
772 mpll->reference_div = RBIOS16(pll_info + 0x28);
773 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
774 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
775
776 if (rev > 10) {
777 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
778 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
779 } else {
780 /* ??? */
781 mpll->pll_in_min = 40;
782 mpll->pll_in_max = 500;
783 }
784
785 /* default sclk/mclk */
786 sclk = RBIOS16(pll_info + 0xa);
787 mclk = RBIOS16(pll_info + 0x8);
788 if (sclk == 0)
789 sclk = 200 * 100;
790 if (mclk == 0)
791 mclk = 200 * 100;
792
793 rdev->clock.default_sclk = sclk;
794 rdev->clock.default_mclk = mclk;
795
796 if (RBIOS32(pll_info + 0x16))
797 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
798 else
799 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
800
801 return true;
802 }
803 return false;
804 }
805
radeon_combios_sideport_present(struct radeon_device * rdev)806 bool radeon_combios_sideport_present(struct radeon_device *rdev)
807 {
808 struct drm_device *dev = rdev_to_drm(rdev);
809 u16 igp_info;
810
811 /* sideport is AMD only */
812 if (rdev->family == CHIP_RS400)
813 return false;
814
815 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
816
817 if (igp_info) {
818 if (RBIOS16(igp_info + 0x4))
819 return true;
820 }
821 return false;
822 }
823
824 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
825 0x00000808, /* r100 */
826 0x00000808, /* rv100 */
827 0x00000808, /* rs100 */
828 0x00000808, /* rv200 */
829 0x00000808, /* rs200 */
830 0x00000808, /* r200 */
831 0x00000808, /* rv250 */
832 0x00000000, /* rs300 */
833 0x00000808, /* rv280 */
834 0x00000808, /* r300 */
835 0x00000808, /* r350 */
836 0x00000808, /* rv350 */
837 0x00000808, /* rv380 */
838 0x00000808, /* r420 */
839 0x00000808, /* r423 */
840 0x00000808, /* rv410 */
841 0x00000000, /* rs400 */
842 0x00000000, /* rs480 */
843 };
844
radeon_legacy_get_primary_dac_info_from_table(struct radeon_device * rdev,struct radeon_encoder_primary_dac * p_dac)845 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
846 struct radeon_encoder_primary_dac *p_dac)
847 {
848 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
849 return;
850 }
851
radeon_combios_get_primary_dac_info(struct radeon_encoder * encoder)852 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
853 radeon_encoder
854 *encoder)
855 {
856 struct drm_device *dev = encoder->base.dev;
857 struct radeon_device *rdev = dev->dev_private;
858 uint16_t dac_info;
859 uint8_t rev, bg, dac;
860 struct radeon_encoder_primary_dac *p_dac;
861 int found = 0;
862
863 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
864 GFP_KERNEL);
865
866 if (!p_dac)
867 return NULL;
868
869 /* check CRT table */
870 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
871 if (dac_info) {
872 rev = RBIOS8(dac_info) & 0x3;
873 if (rev < 2) {
874 bg = RBIOS8(dac_info + 0x2) & 0xf;
875 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
876 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
877 } else {
878 bg = RBIOS8(dac_info + 0x2) & 0xf;
879 dac = RBIOS8(dac_info + 0x3) & 0xf;
880 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
881 }
882 /* if the values are zeros, use the table */
883 if ((dac == 0) || (bg == 0))
884 found = 0;
885 else
886 found = 1;
887 }
888
889 /* quirks */
890 /* Radeon 7000 (RV100) */
891 if (((rdev->pdev->device == 0x5159) &&
892 (rdev->pdev->subsystem_vendor == 0x174B) &&
893 (rdev->pdev->subsystem_device == 0x7c28)) ||
894 /* Radeon 9100 (R200) */
895 ((rdev->pdev->device == 0x514D) &&
896 (rdev->pdev->subsystem_vendor == 0x174B) &&
897 (rdev->pdev->subsystem_device == 0x7149))) {
898 /* vbios value is bad, use the default */
899 found = 0;
900 }
901
902 if (!found) /* fallback to defaults */
903 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
904
905 return p_dac;
906 }
907
908 enum radeon_tv_std
radeon_combios_get_tv_info(struct radeon_device * rdev)909 radeon_combios_get_tv_info(struct radeon_device *rdev)
910 {
911 struct drm_device *dev = rdev_to_drm(rdev);
912 uint16_t tv_info;
913 enum radeon_tv_std tv_std = TV_STD_NTSC;
914
915 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
916 if (tv_info) {
917 if (RBIOS8(tv_info + 6) == 'T') {
918 switch (RBIOS8(tv_info + 7) & 0xf) {
919 case 1:
920 tv_std = TV_STD_NTSC;
921 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
922 break;
923 case 2:
924 tv_std = TV_STD_PAL;
925 DRM_DEBUG_KMS("Default TV standard: PAL\n");
926 break;
927 case 3:
928 tv_std = TV_STD_PAL_M;
929 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
930 break;
931 case 4:
932 tv_std = TV_STD_PAL_60;
933 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
934 break;
935 case 5:
936 tv_std = TV_STD_NTSC_J;
937 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
938 break;
939 case 6:
940 tv_std = TV_STD_SCART_PAL;
941 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
942 break;
943 default:
944 tv_std = TV_STD_NTSC;
945 DRM_DEBUG_KMS
946 ("Unknown TV standard; defaulting to NTSC\n");
947 break;
948 }
949
950 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
951 case 0:
952 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
953 break;
954 case 1:
955 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
956 break;
957 case 2:
958 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
959 break;
960 case 3:
961 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
962 break;
963 default:
964 break;
965 }
966 }
967 }
968 return tv_std;
969 }
970
971 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
972 0x00000000, /* r100 */
973 0x00280000, /* rv100 */
974 0x00000000, /* rs100 */
975 0x00880000, /* rv200 */
976 0x00000000, /* rs200 */
977 0x00000000, /* r200 */
978 0x00770000, /* rv250 */
979 0x00290000, /* rs300 */
980 0x00560000, /* rv280 */
981 0x00780000, /* r300 */
982 0x00770000, /* r350 */
983 0x00780000, /* rv350 */
984 0x00780000, /* rv380 */
985 0x01080000, /* r420 */
986 0x01080000, /* r423 */
987 0x01080000, /* rv410 */
988 0x00780000, /* rs400 */
989 0x00780000, /* rs480 */
990 };
991
radeon_legacy_get_tv_dac_info_from_table(struct radeon_device * rdev,struct radeon_encoder_tv_dac * tv_dac)992 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
993 struct radeon_encoder_tv_dac *tv_dac)
994 {
995 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
996 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
997 tv_dac->ps2_tvdac_adj = 0x00880000;
998 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
999 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1000 return;
1001 }
1002
radeon_combios_get_tv_dac_info(struct radeon_encoder * encoder)1003 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1004 radeon_encoder
1005 *encoder)
1006 {
1007 struct drm_device *dev = encoder->base.dev;
1008 struct radeon_device *rdev = dev->dev_private;
1009 uint16_t dac_info;
1010 uint8_t rev, bg, dac;
1011 struct radeon_encoder_tv_dac *tv_dac;
1012 int found = 0;
1013
1014 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1015 if (!tv_dac)
1016 return NULL;
1017
1018 /* first check TV table */
1019 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1020 if (dac_info) {
1021 rev = RBIOS8(dac_info + 0x3);
1022 if (rev > 4) {
1023 bg = RBIOS8(dac_info + 0xc) & 0xf;
1024 dac = RBIOS8(dac_info + 0xd) & 0xf;
1025 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1026
1027 bg = RBIOS8(dac_info + 0xe) & 0xf;
1028 dac = RBIOS8(dac_info + 0xf) & 0xf;
1029 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1030
1031 bg = RBIOS8(dac_info + 0x10) & 0xf;
1032 dac = RBIOS8(dac_info + 0x11) & 0xf;
1033 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1034 /* if the values are all zeros, use the table */
1035 if (tv_dac->ps2_tvdac_adj)
1036 found = 1;
1037 } else if (rev > 1) {
1038 bg = RBIOS8(dac_info + 0xc) & 0xf;
1039 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1040 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1041
1042 bg = RBIOS8(dac_info + 0xd) & 0xf;
1043 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1044 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1045
1046 bg = RBIOS8(dac_info + 0xe) & 0xf;
1047 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1048 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1049 /* if the values are all zeros, use the table */
1050 if (tv_dac->ps2_tvdac_adj)
1051 found = 1;
1052 }
1053 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1054 }
1055 if (!found) {
1056 /* then check CRT table */
1057 dac_info =
1058 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1059 if (dac_info) {
1060 rev = RBIOS8(dac_info) & 0x3;
1061 if (rev < 2) {
1062 bg = RBIOS8(dac_info + 0x3) & 0xf;
1063 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1064 tv_dac->ps2_tvdac_adj =
1065 (bg << 16) | (dac << 20);
1066 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1067 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1068 /* if the values are all zeros, use the table */
1069 if (tv_dac->ps2_tvdac_adj)
1070 found = 1;
1071 } else {
1072 bg = RBIOS8(dac_info + 0x4) & 0xf;
1073 dac = RBIOS8(dac_info + 0x5) & 0xf;
1074 tv_dac->ps2_tvdac_adj =
1075 (bg << 16) | (dac << 20);
1076 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1077 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1078 /* if the values are all zeros, use the table */
1079 if (tv_dac->ps2_tvdac_adj)
1080 found = 1;
1081 }
1082 } else {
1083 DRM_INFO("No TV DAC info found in BIOS\n");
1084 }
1085 }
1086
1087 if (!found) /* fallback to defaults */
1088 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1089
1090 return tv_dac;
1091 }
1092
radeon_legacy_get_lvds_info_from_regs(struct radeon_device * rdev)1093 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1094 radeon_device
1095 *rdev)
1096 {
1097 struct radeon_encoder_lvds *lvds;
1098 uint32_t fp_vert_stretch, fp_horz_stretch;
1099 uint32_t ppll_div_sel, ppll_val;
1100 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1101
1102 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1103
1104 if (!lvds)
1105 return NULL;
1106
1107 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1108 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1109
1110 /* These should be fail-safe defaults, fingers crossed */
1111 lvds->panel_pwr_delay = 200;
1112 lvds->panel_vcc_delay = 2000;
1113
1114 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1115 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1116 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1117
1118 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1119 lvds->native_mode.vdisplay =
1120 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1121 RADEON_VERT_PANEL_SHIFT) + 1;
1122 else
1123 lvds->native_mode.vdisplay =
1124 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1125
1126 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1127 lvds->native_mode.hdisplay =
1128 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1129 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1130 else
1131 lvds->native_mode.hdisplay =
1132 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1133
1134 if ((lvds->native_mode.hdisplay < 640) ||
1135 (lvds->native_mode.vdisplay < 480)) {
1136 lvds->native_mode.hdisplay = 640;
1137 lvds->native_mode.vdisplay = 480;
1138 }
1139
1140 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1141 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1142 if ((ppll_val & 0x000707ff) == 0x1bb)
1143 lvds->use_bios_dividers = false;
1144 else {
1145 lvds->panel_ref_divider =
1146 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1147 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1148 lvds->panel_fb_divider = ppll_val & 0x7ff;
1149
1150 if ((lvds->panel_ref_divider != 0) &&
1151 (lvds->panel_fb_divider > 3))
1152 lvds->use_bios_dividers = true;
1153 }
1154 lvds->panel_vcc_delay = 200;
1155
1156 DRM_INFO("Panel info derived from registers\n");
1157 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1158 lvds->native_mode.vdisplay);
1159
1160 return lvds;
1161 }
1162
radeon_combios_get_lvds_info(struct radeon_encoder * encoder)1163 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1164 *encoder)
1165 {
1166 struct drm_device *dev = encoder->base.dev;
1167 struct radeon_device *rdev = dev->dev_private;
1168 uint16_t lcd_info;
1169 uint32_t panel_setup;
1170 char stmp[30];
1171 int tmp, i;
1172 struct radeon_encoder_lvds *lvds = NULL;
1173
1174 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1175
1176 if (lcd_info) {
1177 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1178
1179 if (!lvds)
1180 return NULL;
1181
1182 for (i = 0; i < 24; i++)
1183 stmp[i] = RBIOS8(lcd_info + i + 1);
1184 stmp[24] = 0;
1185
1186 DRM_INFO("Panel ID String: %s\n", stmp);
1187
1188 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1189 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1190
1191 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1192 lvds->native_mode.vdisplay);
1193
1194 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1195 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1196
1197 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1198 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1199 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1200
1201 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1202 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1203 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1204 if ((lvds->panel_ref_divider != 0) &&
1205 (lvds->panel_fb_divider > 3))
1206 lvds->use_bios_dividers = true;
1207
1208 panel_setup = RBIOS32(lcd_info + 0x39);
1209 lvds->lvds_gen_cntl = 0xff00;
1210 if (panel_setup & 0x1)
1211 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1212
1213 if ((panel_setup >> 4) & 0x1)
1214 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1215
1216 switch ((panel_setup >> 8) & 0x7) {
1217 case 0:
1218 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1219 break;
1220 case 1:
1221 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1222 break;
1223 case 2:
1224 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1225 break;
1226 default:
1227 break;
1228 }
1229
1230 if ((panel_setup >> 16) & 0x1)
1231 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1232
1233 if ((panel_setup >> 17) & 0x1)
1234 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1235
1236 if ((panel_setup >> 18) & 0x1)
1237 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1238
1239 if ((panel_setup >> 23) & 0x1)
1240 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1241
1242 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1243
1244 for (i = 0; i < 32; i++) {
1245 tmp = RBIOS16(lcd_info + 64 + i * 2);
1246 if (tmp == 0)
1247 break;
1248
1249 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1250 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1251 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1252
1253 if (hss > lvds->native_mode.hdisplay)
1254 hss = (10 - 1) * 8;
1255
1256 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1257 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1258 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1259 hss;
1260 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1261 (RBIOS8(tmp + 23) * 8);
1262
1263 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1264 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1265 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1266 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1267 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1268 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1269
1270 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1271 lvds->native_mode.flags = 0;
1272 /* set crtc values */
1273 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1274
1275 }
1276 }
1277 } else {
1278 DRM_INFO("No panel info found in BIOS\n");
1279 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1280 }
1281
1282 if (lvds)
1283 encoder->native_mode = lvds->native_mode;
1284 return lvds;
1285 }
1286
1287 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1288 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1289 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1290 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1291 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1292 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1293 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1294 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1295 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1296 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1297 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1298 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1299 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1300 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1301 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1302 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1303 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1304 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1305 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1306 };
1307
radeon_legacy_get_tmds_info_from_table(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1308 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1309 struct radeon_encoder_int_tmds *tmds)
1310 {
1311 struct drm_device *dev = encoder->base.dev;
1312 struct radeon_device *rdev = dev->dev_private;
1313 int i;
1314
1315 for (i = 0; i < 4; i++) {
1316 tmds->tmds_pll[i].value =
1317 default_tmds_pll[rdev->family][i].value;
1318 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1319 }
1320
1321 return true;
1322 }
1323
radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1324 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1325 struct radeon_encoder_int_tmds *tmds)
1326 {
1327 struct drm_device *dev = encoder->base.dev;
1328 struct radeon_device *rdev = dev->dev_private;
1329 uint16_t tmds_info;
1330 int i, n;
1331 uint8_t ver;
1332
1333 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1334
1335 if (tmds_info) {
1336 ver = RBIOS8(tmds_info);
1337 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1338 if (ver == 3) {
1339 n = RBIOS8(tmds_info + 5) + 1;
1340 if (n > 4)
1341 n = 4;
1342 for (i = 0; i < n; i++) {
1343 tmds->tmds_pll[i].value =
1344 RBIOS32(tmds_info + i * 10 + 0x08);
1345 tmds->tmds_pll[i].freq =
1346 RBIOS16(tmds_info + i * 10 + 0x10);
1347 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1348 tmds->tmds_pll[i].freq,
1349 tmds->tmds_pll[i].value);
1350 }
1351 } else if (ver == 4) {
1352 int stride = 0;
1353 n = RBIOS8(tmds_info + 5) + 1;
1354 if (n > 4)
1355 n = 4;
1356 for (i = 0; i < n; i++) {
1357 tmds->tmds_pll[i].value =
1358 RBIOS32(tmds_info + stride + 0x08);
1359 tmds->tmds_pll[i].freq =
1360 RBIOS16(tmds_info + stride + 0x10);
1361 if (i == 0)
1362 stride += 10;
1363 else
1364 stride += 6;
1365 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1366 tmds->tmds_pll[i].freq,
1367 tmds->tmds_pll[i].value);
1368 }
1369 }
1370 } else {
1371 DRM_INFO("No TMDS info found in BIOS\n");
1372 return false;
1373 }
1374 return true;
1375 }
1376
radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder * encoder,struct radeon_encoder_ext_tmds * tmds)1377 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1378 struct radeon_encoder_ext_tmds *tmds)
1379 {
1380 struct drm_device *dev = encoder->base.dev;
1381 struct radeon_device *rdev = dev->dev_private;
1382 struct radeon_i2c_bus_rec i2c_bus;
1383
1384 /* default for macs */
1385 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1386 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1387
1388 /* XXX some macs have duallink chips */
1389 switch (rdev->mode_info.connector_table) {
1390 case CT_POWERBOOK_EXTERNAL:
1391 case CT_MINI_EXTERNAL:
1392 default:
1393 tmds->dvo_chip = DVO_SIL164;
1394 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1395 break;
1396 }
1397
1398 return true;
1399 }
1400
radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder * encoder,struct radeon_encoder_ext_tmds * tmds)1401 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1402 struct radeon_encoder_ext_tmds *tmds)
1403 {
1404 struct drm_device *dev = encoder->base.dev;
1405 struct radeon_device *rdev = dev->dev_private;
1406 uint16_t offset;
1407 uint8_t ver;
1408 enum radeon_combios_ddc gpio;
1409 struct radeon_i2c_bus_rec i2c_bus;
1410
1411 tmds->i2c_bus = NULL;
1412 if (rdev->flags & RADEON_IS_IGP) {
1413 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1414 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1415 tmds->dvo_chip = DVO_SIL164;
1416 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1417 } else {
1418 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1419 if (offset) {
1420 ver = RBIOS8(offset);
1421 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1422 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1423 tmds->slave_addr >>= 1; /* 7 bit addressing */
1424 gpio = RBIOS8(offset + 4 + 3);
1425 if (gpio == DDC_LCD) {
1426 /* MM i2c */
1427 i2c_bus.valid = true;
1428 i2c_bus.hw_capable = true;
1429 i2c_bus.mm_i2c = true;
1430 i2c_bus.i2c_id = 0xa0;
1431 } else
1432 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1433 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1434 }
1435 }
1436
1437 if (!tmds->i2c_bus) {
1438 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1439 return false;
1440 }
1441
1442 return true;
1443 }
1444
radeon_get_legacy_connector_info_from_table(struct drm_device * dev)1445 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1446 {
1447 struct radeon_device *rdev = dev->dev_private;
1448 struct radeon_i2c_bus_rec ddc_i2c;
1449 struct radeon_hpd hpd;
1450
1451 rdev->mode_info.connector_table = radeon_connector_table;
1452 if (rdev->mode_info.connector_table == CT_NONE) {
1453 #ifdef CONFIG_PPC_PMAC
1454 if (of_machine_is_compatible("PowerBook3,3")) {
1455 /* powerbook with VGA */
1456 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1457 } else if (of_machine_is_compatible("PowerBook3,4") ||
1458 of_machine_is_compatible("PowerBook3,5")) {
1459 /* powerbook with internal tmds */
1460 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1461 } else if (of_machine_is_compatible("PowerBook5,1") ||
1462 of_machine_is_compatible("PowerBook5,2") ||
1463 of_machine_is_compatible("PowerBook5,3") ||
1464 of_machine_is_compatible("PowerBook5,4") ||
1465 of_machine_is_compatible("PowerBook5,5")) {
1466 /* powerbook with external single link tmds (sil164) */
1467 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1468 } else if (of_machine_is_compatible("PowerBook5,6")) {
1469 /* powerbook with external dual or single link tmds */
1470 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1471 } else if (of_machine_is_compatible("PowerBook5,7") ||
1472 of_machine_is_compatible("PowerBook5,8") ||
1473 of_machine_is_compatible("PowerBook5,9")) {
1474 /* PowerBook6,2 ? */
1475 /* powerbook with external dual link tmds (sil1178?) */
1476 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1477 } else if (of_machine_is_compatible("PowerBook4,1") ||
1478 of_machine_is_compatible("PowerBook4,2") ||
1479 of_machine_is_compatible("PowerBook4,3") ||
1480 of_machine_is_compatible("PowerBook6,3") ||
1481 of_machine_is_compatible("PowerBook6,5") ||
1482 of_machine_is_compatible("PowerBook6,7")) {
1483 /* ibook */
1484 rdev->mode_info.connector_table = CT_IBOOK;
1485 } else if (of_machine_is_compatible("PowerMac3,5")) {
1486 /* PowerMac G4 Silver radeon 7500 */
1487 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1488 } else if (of_machine_is_compatible("PowerMac4,4")) {
1489 /* emac */
1490 rdev->mode_info.connector_table = CT_EMAC;
1491 } else if (of_machine_is_compatible("PowerMac10,1")) {
1492 /* mini with internal tmds */
1493 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1494 } else if (of_machine_is_compatible("PowerMac10,2")) {
1495 /* mini with external tmds */
1496 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1497 } else if (of_machine_is_compatible("PowerMac12,1")) {
1498 /* PowerMac8,1 ? */
1499 /* imac g5 isight */
1500 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1501 } else if ((rdev->pdev->device == 0x4a48) &&
1502 (rdev->pdev->subsystem_vendor == 0x1002) &&
1503 (rdev->pdev->subsystem_device == 0x4a48)) {
1504 /* Mac X800 */
1505 rdev->mode_info.connector_table = CT_MAC_X800;
1506 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1507 of_machine_is_compatible("PowerMac7,3")) &&
1508 (rdev->pdev->device == 0x4150) &&
1509 (rdev->pdev->subsystem_vendor == 0x1002) &&
1510 (rdev->pdev->subsystem_device == 0x4150)) {
1511 /* Mac G5 tower 9600 */
1512 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1513 } else if ((rdev->pdev->device == 0x4c66) &&
1514 (rdev->pdev->subsystem_vendor == 0x1002) &&
1515 (rdev->pdev->subsystem_device == 0x4c66)) {
1516 /* SAM440ep RV250 embedded board */
1517 rdev->mode_info.connector_table = CT_SAM440EP;
1518 } else
1519 #endif /* CONFIG_PPC_PMAC */
1520 #ifdef CONFIG_PPC64
1521 if (ASIC_IS_RN50(rdev))
1522 rdev->mode_info.connector_table = CT_RN50_POWER;
1523 else
1524 #endif
1525 rdev->mode_info.connector_table = CT_GENERIC;
1526 }
1527
1528 switch (rdev->mode_info.connector_table) {
1529 case CT_GENERIC:
1530 DRM_INFO("Connector Table: %d (generic)\n",
1531 rdev->mode_info.connector_table);
1532 /* these are the most common settings */
1533 if (rdev->flags & RADEON_SINGLE_CRTC) {
1534 /* VGA - primary dac */
1535 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1536 hpd.hpd = RADEON_HPD_NONE;
1537 radeon_add_legacy_encoder(dev,
1538 radeon_get_encoder_enum(dev,
1539 ATOM_DEVICE_CRT1_SUPPORT,
1540 1),
1541 ATOM_DEVICE_CRT1_SUPPORT);
1542 radeon_add_legacy_connector(dev, 0,
1543 ATOM_DEVICE_CRT1_SUPPORT,
1544 DRM_MODE_CONNECTOR_VGA,
1545 &ddc_i2c,
1546 CONNECTOR_OBJECT_ID_VGA,
1547 &hpd);
1548 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1549 /* LVDS */
1550 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1551 hpd.hpd = RADEON_HPD_NONE;
1552 radeon_add_legacy_encoder(dev,
1553 radeon_get_encoder_enum(dev,
1554 ATOM_DEVICE_LCD1_SUPPORT,
1555 0),
1556 ATOM_DEVICE_LCD1_SUPPORT);
1557 radeon_add_legacy_connector(dev, 0,
1558 ATOM_DEVICE_LCD1_SUPPORT,
1559 DRM_MODE_CONNECTOR_LVDS,
1560 &ddc_i2c,
1561 CONNECTOR_OBJECT_ID_LVDS,
1562 &hpd);
1563
1564 /* VGA - primary dac */
1565 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1566 hpd.hpd = RADEON_HPD_NONE;
1567 radeon_add_legacy_encoder(dev,
1568 radeon_get_encoder_enum(dev,
1569 ATOM_DEVICE_CRT1_SUPPORT,
1570 1),
1571 ATOM_DEVICE_CRT1_SUPPORT);
1572 radeon_add_legacy_connector(dev, 1,
1573 ATOM_DEVICE_CRT1_SUPPORT,
1574 DRM_MODE_CONNECTOR_VGA,
1575 &ddc_i2c,
1576 CONNECTOR_OBJECT_ID_VGA,
1577 &hpd);
1578 } else {
1579 /* DVI-I - tv dac, int tmds */
1580 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1581 hpd.hpd = RADEON_HPD_1;
1582 radeon_add_legacy_encoder(dev,
1583 radeon_get_encoder_enum(dev,
1584 ATOM_DEVICE_DFP1_SUPPORT,
1585 0),
1586 ATOM_DEVICE_DFP1_SUPPORT);
1587 radeon_add_legacy_encoder(dev,
1588 radeon_get_encoder_enum(dev,
1589 ATOM_DEVICE_CRT2_SUPPORT,
1590 2),
1591 ATOM_DEVICE_CRT2_SUPPORT);
1592 radeon_add_legacy_connector(dev, 0,
1593 ATOM_DEVICE_DFP1_SUPPORT |
1594 ATOM_DEVICE_CRT2_SUPPORT,
1595 DRM_MODE_CONNECTOR_DVII,
1596 &ddc_i2c,
1597 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1598 &hpd);
1599
1600 /* VGA - primary dac */
1601 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1602 hpd.hpd = RADEON_HPD_NONE;
1603 radeon_add_legacy_encoder(dev,
1604 radeon_get_encoder_enum(dev,
1605 ATOM_DEVICE_CRT1_SUPPORT,
1606 1),
1607 ATOM_DEVICE_CRT1_SUPPORT);
1608 radeon_add_legacy_connector(dev, 1,
1609 ATOM_DEVICE_CRT1_SUPPORT,
1610 DRM_MODE_CONNECTOR_VGA,
1611 &ddc_i2c,
1612 CONNECTOR_OBJECT_ID_VGA,
1613 &hpd);
1614 }
1615
1616 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1617 /* TV - tv dac */
1618 ddc_i2c.valid = false;
1619 hpd.hpd = RADEON_HPD_NONE;
1620 radeon_add_legacy_encoder(dev,
1621 radeon_get_encoder_enum(dev,
1622 ATOM_DEVICE_TV1_SUPPORT,
1623 2),
1624 ATOM_DEVICE_TV1_SUPPORT);
1625 radeon_add_legacy_connector(dev, 2,
1626 ATOM_DEVICE_TV1_SUPPORT,
1627 DRM_MODE_CONNECTOR_SVIDEO,
1628 &ddc_i2c,
1629 CONNECTOR_OBJECT_ID_SVIDEO,
1630 &hpd);
1631 }
1632 break;
1633 case CT_IBOOK:
1634 DRM_INFO("Connector Table: %d (ibook)\n",
1635 rdev->mode_info.connector_table);
1636 /* LVDS */
1637 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1638 hpd.hpd = RADEON_HPD_NONE;
1639 radeon_add_legacy_encoder(dev,
1640 radeon_get_encoder_enum(dev,
1641 ATOM_DEVICE_LCD1_SUPPORT,
1642 0),
1643 ATOM_DEVICE_LCD1_SUPPORT);
1644 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1645 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1646 CONNECTOR_OBJECT_ID_LVDS,
1647 &hpd);
1648 /* VGA - TV DAC */
1649 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1650 hpd.hpd = RADEON_HPD_NONE;
1651 radeon_add_legacy_encoder(dev,
1652 radeon_get_encoder_enum(dev,
1653 ATOM_DEVICE_CRT2_SUPPORT,
1654 2),
1655 ATOM_DEVICE_CRT2_SUPPORT);
1656 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1657 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1658 CONNECTOR_OBJECT_ID_VGA,
1659 &hpd);
1660 /* TV - TV DAC */
1661 ddc_i2c.valid = false;
1662 hpd.hpd = RADEON_HPD_NONE;
1663 radeon_add_legacy_encoder(dev,
1664 radeon_get_encoder_enum(dev,
1665 ATOM_DEVICE_TV1_SUPPORT,
1666 2),
1667 ATOM_DEVICE_TV1_SUPPORT);
1668 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1669 DRM_MODE_CONNECTOR_SVIDEO,
1670 &ddc_i2c,
1671 CONNECTOR_OBJECT_ID_SVIDEO,
1672 &hpd);
1673 break;
1674 case CT_POWERBOOK_EXTERNAL:
1675 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1676 rdev->mode_info.connector_table);
1677 /* LVDS */
1678 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1679 hpd.hpd = RADEON_HPD_NONE;
1680 radeon_add_legacy_encoder(dev,
1681 radeon_get_encoder_enum(dev,
1682 ATOM_DEVICE_LCD1_SUPPORT,
1683 0),
1684 ATOM_DEVICE_LCD1_SUPPORT);
1685 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1686 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1687 CONNECTOR_OBJECT_ID_LVDS,
1688 &hpd);
1689 /* DVI-I - primary dac, ext tmds */
1690 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1691 hpd.hpd = RADEON_HPD_2; /* ??? */
1692 radeon_add_legacy_encoder(dev,
1693 radeon_get_encoder_enum(dev,
1694 ATOM_DEVICE_DFP2_SUPPORT,
1695 0),
1696 ATOM_DEVICE_DFP2_SUPPORT);
1697 radeon_add_legacy_encoder(dev,
1698 radeon_get_encoder_enum(dev,
1699 ATOM_DEVICE_CRT1_SUPPORT,
1700 1),
1701 ATOM_DEVICE_CRT1_SUPPORT);
1702 /* XXX some are SL */
1703 radeon_add_legacy_connector(dev, 1,
1704 ATOM_DEVICE_DFP2_SUPPORT |
1705 ATOM_DEVICE_CRT1_SUPPORT,
1706 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1707 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1708 &hpd);
1709 /* TV - TV DAC */
1710 ddc_i2c.valid = false;
1711 hpd.hpd = RADEON_HPD_NONE;
1712 radeon_add_legacy_encoder(dev,
1713 radeon_get_encoder_enum(dev,
1714 ATOM_DEVICE_TV1_SUPPORT,
1715 2),
1716 ATOM_DEVICE_TV1_SUPPORT);
1717 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1718 DRM_MODE_CONNECTOR_SVIDEO,
1719 &ddc_i2c,
1720 CONNECTOR_OBJECT_ID_SVIDEO,
1721 &hpd);
1722 break;
1723 case CT_POWERBOOK_INTERNAL:
1724 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1725 rdev->mode_info.connector_table);
1726 /* LVDS */
1727 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1728 hpd.hpd = RADEON_HPD_NONE;
1729 radeon_add_legacy_encoder(dev,
1730 radeon_get_encoder_enum(dev,
1731 ATOM_DEVICE_LCD1_SUPPORT,
1732 0),
1733 ATOM_DEVICE_LCD1_SUPPORT);
1734 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1735 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1736 CONNECTOR_OBJECT_ID_LVDS,
1737 &hpd);
1738 /* DVI-I - primary dac, int tmds */
1739 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1740 hpd.hpd = RADEON_HPD_1; /* ??? */
1741 radeon_add_legacy_encoder(dev,
1742 radeon_get_encoder_enum(dev,
1743 ATOM_DEVICE_DFP1_SUPPORT,
1744 0),
1745 ATOM_DEVICE_DFP1_SUPPORT);
1746 radeon_add_legacy_encoder(dev,
1747 radeon_get_encoder_enum(dev,
1748 ATOM_DEVICE_CRT1_SUPPORT,
1749 1),
1750 ATOM_DEVICE_CRT1_SUPPORT);
1751 radeon_add_legacy_connector(dev, 1,
1752 ATOM_DEVICE_DFP1_SUPPORT |
1753 ATOM_DEVICE_CRT1_SUPPORT,
1754 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1755 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1756 &hpd);
1757 /* TV - TV DAC */
1758 ddc_i2c.valid = false;
1759 hpd.hpd = RADEON_HPD_NONE;
1760 radeon_add_legacy_encoder(dev,
1761 radeon_get_encoder_enum(dev,
1762 ATOM_DEVICE_TV1_SUPPORT,
1763 2),
1764 ATOM_DEVICE_TV1_SUPPORT);
1765 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1766 DRM_MODE_CONNECTOR_SVIDEO,
1767 &ddc_i2c,
1768 CONNECTOR_OBJECT_ID_SVIDEO,
1769 &hpd);
1770 break;
1771 case CT_POWERBOOK_VGA:
1772 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1773 rdev->mode_info.connector_table);
1774 /* LVDS */
1775 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1776 hpd.hpd = RADEON_HPD_NONE;
1777 radeon_add_legacy_encoder(dev,
1778 radeon_get_encoder_enum(dev,
1779 ATOM_DEVICE_LCD1_SUPPORT,
1780 0),
1781 ATOM_DEVICE_LCD1_SUPPORT);
1782 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1783 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1784 CONNECTOR_OBJECT_ID_LVDS,
1785 &hpd);
1786 /* VGA - primary dac */
1787 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1788 hpd.hpd = RADEON_HPD_NONE;
1789 radeon_add_legacy_encoder(dev,
1790 radeon_get_encoder_enum(dev,
1791 ATOM_DEVICE_CRT1_SUPPORT,
1792 1),
1793 ATOM_DEVICE_CRT1_SUPPORT);
1794 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1795 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1796 CONNECTOR_OBJECT_ID_VGA,
1797 &hpd);
1798 /* TV - TV DAC */
1799 ddc_i2c.valid = false;
1800 hpd.hpd = RADEON_HPD_NONE;
1801 radeon_add_legacy_encoder(dev,
1802 radeon_get_encoder_enum(dev,
1803 ATOM_DEVICE_TV1_SUPPORT,
1804 2),
1805 ATOM_DEVICE_TV1_SUPPORT);
1806 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1807 DRM_MODE_CONNECTOR_SVIDEO,
1808 &ddc_i2c,
1809 CONNECTOR_OBJECT_ID_SVIDEO,
1810 &hpd);
1811 break;
1812 case CT_MINI_EXTERNAL:
1813 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1814 rdev->mode_info.connector_table);
1815 /* DVI-I - tv dac, ext tmds */
1816 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1817 hpd.hpd = RADEON_HPD_2; /* ??? */
1818 radeon_add_legacy_encoder(dev,
1819 radeon_get_encoder_enum(dev,
1820 ATOM_DEVICE_DFP2_SUPPORT,
1821 0),
1822 ATOM_DEVICE_DFP2_SUPPORT);
1823 radeon_add_legacy_encoder(dev,
1824 radeon_get_encoder_enum(dev,
1825 ATOM_DEVICE_CRT2_SUPPORT,
1826 2),
1827 ATOM_DEVICE_CRT2_SUPPORT);
1828 /* XXX are any DL? */
1829 radeon_add_legacy_connector(dev, 0,
1830 ATOM_DEVICE_DFP2_SUPPORT |
1831 ATOM_DEVICE_CRT2_SUPPORT,
1832 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1833 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1834 &hpd);
1835 /* TV - TV DAC */
1836 ddc_i2c.valid = false;
1837 hpd.hpd = RADEON_HPD_NONE;
1838 radeon_add_legacy_encoder(dev,
1839 radeon_get_encoder_enum(dev,
1840 ATOM_DEVICE_TV1_SUPPORT,
1841 2),
1842 ATOM_DEVICE_TV1_SUPPORT);
1843 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1844 DRM_MODE_CONNECTOR_SVIDEO,
1845 &ddc_i2c,
1846 CONNECTOR_OBJECT_ID_SVIDEO,
1847 &hpd);
1848 break;
1849 case CT_MINI_INTERNAL:
1850 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1851 rdev->mode_info.connector_table);
1852 /* DVI-I - tv dac, int tmds */
1853 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1854 hpd.hpd = RADEON_HPD_1; /* ??? */
1855 radeon_add_legacy_encoder(dev,
1856 radeon_get_encoder_enum(dev,
1857 ATOM_DEVICE_DFP1_SUPPORT,
1858 0),
1859 ATOM_DEVICE_DFP1_SUPPORT);
1860 radeon_add_legacy_encoder(dev,
1861 radeon_get_encoder_enum(dev,
1862 ATOM_DEVICE_CRT2_SUPPORT,
1863 2),
1864 ATOM_DEVICE_CRT2_SUPPORT);
1865 radeon_add_legacy_connector(dev, 0,
1866 ATOM_DEVICE_DFP1_SUPPORT |
1867 ATOM_DEVICE_CRT2_SUPPORT,
1868 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1869 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1870 &hpd);
1871 /* TV - TV DAC */
1872 ddc_i2c.valid = false;
1873 hpd.hpd = RADEON_HPD_NONE;
1874 radeon_add_legacy_encoder(dev,
1875 radeon_get_encoder_enum(dev,
1876 ATOM_DEVICE_TV1_SUPPORT,
1877 2),
1878 ATOM_DEVICE_TV1_SUPPORT);
1879 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1880 DRM_MODE_CONNECTOR_SVIDEO,
1881 &ddc_i2c,
1882 CONNECTOR_OBJECT_ID_SVIDEO,
1883 &hpd);
1884 break;
1885 case CT_IMAC_G5_ISIGHT:
1886 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1887 rdev->mode_info.connector_table);
1888 /* DVI-D - int tmds */
1889 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1890 hpd.hpd = RADEON_HPD_1; /* ??? */
1891 radeon_add_legacy_encoder(dev,
1892 radeon_get_encoder_enum(dev,
1893 ATOM_DEVICE_DFP1_SUPPORT,
1894 0),
1895 ATOM_DEVICE_DFP1_SUPPORT);
1896 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1897 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1898 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1899 &hpd);
1900 /* VGA - tv dac */
1901 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1902 hpd.hpd = RADEON_HPD_NONE;
1903 radeon_add_legacy_encoder(dev,
1904 radeon_get_encoder_enum(dev,
1905 ATOM_DEVICE_CRT2_SUPPORT,
1906 2),
1907 ATOM_DEVICE_CRT2_SUPPORT);
1908 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1909 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1910 CONNECTOR_OBJECT_ID_VGA,
1911 &hpd);
1912 /* TV - TV DAC */
1913 ddc_i2c.valid = false;
1914 hpd.hpd = RADEON_HPD_NONE;
1915 radeon_add_legacy_encoder(dev,
1916 radeon_get_encoder_enum(dev,
1917 ATOM_DEVICE_TV1_SUPPORT,
1918 2),
1919 ATOM_DEVICE_TV1_SUPPORT);
1920 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1921 DRM_MODE_CONNECTOR_SVIDEO,
1922 &ddc_i2c,
1923 CONNECTOR_OBJECT_ID_SVIDEO,
1924 &hpd);
1925 break;
1926 case CT_EMAC:
1927 DRM_INFO("Connector Table: %d (emac)\n",
1928 rdev->mode_info.connector_table);
1929 /* VGA - primary dac */
1930 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1931 hpd.hpd = RADEON_HPD_NONE;
1932 radeon_add_legacy_encoder(dev,
1933 radeon_get_encoder_enum(dev,
1934 ATOM_DEVICE_CRT1_SUPPORT,
1935 1),
1936 ATOM_DEVICE_CRT1_SUPPORT);
1937 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1938 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1939 CONNECTOR_OBJECT_ID_VGA,
1940 &hpd);
1941 /* VGA - tv dac */
1942 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1943 hpd.hpd = RADEON_HPD_NONE;
1944 radeon_add_legacy_encoder(dev,
1945 radeon_get_encoder_enum(dev,
1946 ATOM_DEVICE_CRT2_SUPPORT,
1947 2),
1948 ATOM_DEVICE_CRT2_SUPPORT);
1949 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1950 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1951 CONNECTOR_OBJECT_ID_VGA,
1952 &hpd);
1953 /* TV - TV DAC */
1954 ddc_i2c.valid = false;
1955 hpd.hpd = RADEON_HPD_NONE;
1956 radeon_add_legacy_encoder(dev,
1957 radeon_get_encoder_enum(dev,
1958 ATOM_DEVICE_TV1_SUPPORT,
1959 2),
1960 ATOM_DEVICE_TV1_SUPPORT);
1961 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1962 DRM_MODE_CONNECTOR_SVIDEO,
1963 &ddc_i2c,
1964 CONNECTOR_OBJECT_ID_SVIDEO,
1965 &hpd);
1966 break;
1967 case CT_RN50_POWER:
1968 DRM_INFO("Connector Table: %d (rn50-power)\n",
1969 rdev->mode_info.connector_table);
1970 /* VGA - primary dac */
1971 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1972 hpd.hpd = RADEON_HPD_NONE;
1973 radeon_add_legacy_encoder(dev,
1974 radeon_get_encoder_enum(dev,
1975 ATOM_DEVICE_CRT1_SUPPORT,
1976 1),
1977 ATOM_DEVICE_CRT1_SUPPORT);
1978 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1979 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1980 CONNECTOR_OBJECT_ID_VGA,
1981 &hpd);
1982 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1983 hpd.hpd = RADEON_HPD_NONE;
1984 radeon_add_legacy_encoder(dev,
1985 radeon_get_encoder_enum(dev,
1986 ATOM_DEVICE_CRT2_SUPPORT,
1987 2),
1988 ATOM_DEVICE_CRT2_SUPPORT);
1989 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1990 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1991 CONNECTOR_OBJECT_ID_VGA,
1992 &hpd);
1993 break;
1994 case CT_MAC_X800:
1995 DRM_INFO("Connector Table: %d (mac x800)\n",
1996 rdev->mode_info.connector_table);
1997 /* DVI - primary dac, internal tmds */
1998 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1999 hpd.hpd = RADEON_HPD_1; /* ??? */
2000 radeon_add_legacy_encoder(dev,
2001 radeon_get_encoder_enum(dev,
2002 ATOM_DEVICE_DFP1_SUPPORT,
2003 0),
2004 ATOM_DEVICE_DFP1_SUPPORT);
2005 radeon_add_legacy_encoder(dev,
2006 radeon_get_encoder_enum(dev,
2007 ATOM_DEVICE_CRT1_SUPPORT,
2008 1),
2009 ATOM_DEVICE_CRT1_SUPPORT);
2010 radeon_add_legacy_connector(dev, 0,
2011 ATOM_DEVICE_DFP1_SUPPORT |
2012 ATOM_DEVICE_CRT1_SUPPORT,
2013 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2014 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2015 &hpd);
2016 /* DVI - tv dac, dvo */
2017 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2018 hpd.hpd = RADEON_HPD_2; /* ??? */
2019 radeon_add_legacy_encoder(dev,
2020 radeon_get_encoder_enum(dev,
2021 ATOM_DEVICE_DFP2_SUPPORT,
2022 0),
2023 ATOM_DEVICE_DFP2_SUPPORT);
2024 radeon_add_legacy_encoder(dev,
2025 radeon_get_encoder_enum(dev,
2026 ATOM_DEVICE_CRT2_SUPPORT,
2027 2),
2028 ATOM_DEVICE_CRT2_SUPPORT);
2029 radeon_add_legacy_connector(dev, 1,
2030 ATOM_DEVICE_DFP2_SUPPORT |
2031 ATOM_DEVICE_CRT2_SUPPORT,
2032 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2033 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2034 &hpd);
2035 break;
2036 case CT_MAC_G5_9600:
2037 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2038 rdev->mode_info.connector_table);
2039 /* DVI - tv dac, dvo */
2040 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2041 hpd.hpd = RADEON_HPD_1; /* ??? */
2042 radeon_add_legacy_encoder(dev,
2043 radeon_get_encoder_enum(dev,
2044 ATOM_DEVICE_DFP2_SUPPORT,
2045 0),
2046 ATOM_DEVICE_DFP2_SUPPORT);
2047 radeon_add_legacy_encoder(dev,
2048 radeon_get_encoder_enum(dev,
2049 ATOM_DEVICE_CRT2_SUPPORT,
2050 2),
2051 ATOM_DEVICE_CRT2_SUPPORT);
2052 radeon_add_legacy_connector(dev, 0,
2053 ATOM_DEVICE_DFP2_SUPPORT |
2054 ATOM_DEVICE_CRT2_SUPPORT,
2055 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2056 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2057 &hpd);
2058 /* ADC - primary dac, internal tmds */
2059 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2060 hpd.hpd = RADEON_HPD_2; /* ??? */
2061 radeon_add_legacy_encoder(dev,
2062 radeon_get_encoder_enum(dev,
2063 ATOM_DEVICE_DFP1_SUPPORT,
2064 0),
2065 ATOM_DEVICE_DFP1_SUPPORT);
2066 radeon_add_legacy_encoder(dev,
2067 radeon_get_encoder_enum(dev,
2068 ATOM_DEVICE_CRT1_SUPPORT,
2069 1),
2070 ATOM_DEVICE_CRT1_SUPPORT);
2071 radeon_add_legacy_connector(dev, 1,
2072 ATOM_DEVICE_DFP1_SUPPORT |
2073 ATOM_DEVICE_CRT1_SUPPORT,
2074 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2075 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2076 &hpd);
2077 /* TV - TV DAC */
2078 ddc_i2c.valid = false;
2079 hpd.hpd = RADEON_HPD_NONE;
2080 radeon_add_legacy_encoder(dev,
2081 radeon_get_encoder_enum(dev,
2082 ATOM_DEVICE_TV1_SUPPORT,
2083 2),
2084 ATOM_DEVICE_TV1_SUPPORT);
2085 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2086 DRM_MODE_CONNECTOR_SVIDEO,
2087 &ddc_i2c,
2088 CONNECTOR_OBJECT_ID_SVIDEO,
2089 &hpd);
2090 break;
2091 case CT_SAM440EP:
2092 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2093 rdev->mode_info.connector_table);
2094 /* LVDS */
2095 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2096 hpd.hpd = RADEON_HPD_NONE;
2097 radeon_add_legacy_encoder(dev,
2098 radeon_get_encoder_enum(dev,
2099 ATOM_DEVICE_LCD1_SUPPORT,
2100 0),
2101 ATOM_DEVICE_LCD1_SUPPORT);
2102 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2103 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2104 CONNECTOR_OBJECT_ID_LVDS,
2105 &hpd);
2106 /* DVI-I - secondary dac, int tmds */
2107 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2108 hpd.hpd = RADEON_HPD_1; /* ??? */
2109 radeon_add_legacy_encoder(dev,
2110 radeon_get_encoder_enum(dev,
2111 ATOM_DEVICE_DFP1_SUPPORT,
2112 0),
2113 ATOM_DEVICE_DFP1_SUPPORT);
2114 radeon_add_legacy_encoder(dev,
2115 radeon_get_encoder_enum(dev,
2116 ATOM_DEVICE_CRT2_SUPPORT,
2117 2),
2118 ATOM_DEVICE_CRT2_SUPPORT);
2119 radeon_add_legacy_connector(dev, 1,
2120 ATOM_DEVICE_DFP1_SUPPORT |
2121 ATOM_DEVICE_CRT2_SUPPORT,
2122 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2123 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2124 &hpd);
2125 /* VGA - primary dac */
2126 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2127 hpd.hpd = RADEON_HPD_NONE;
2128 radeon_add_legacy_encoder(dev,
2129 radeon_get_encoder_enum(dev,
2130 ATOM_DEVICE_CRT1_SUPPORT,
2131 1),
2132 ATOM_DEVICE_CRT1_SUPPORT);
2133 radeon_add_legacy_connector(dev, 2,
2134 ATOM_DEVICE_CRT1_SUPPORT,
2135 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2136 CONNECTOR_OBJECT_ID_VGA,
2137 &hpd);
2138 /* TV - TV DAC */
2139 ddc_i2c.valid = false;
2140 hpd.hpd = RADEON_HPD_NONE;
2141 radeon_add_legacy_encoder(dev,
2142 radeon_get_encoder_enum(dev,
2143 ATOM_DEVICE_TV1_SUPPORT,
2144 2),
2145 ATOM_DEVICE_TV1_SUPPORT);
2146 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2147 DRM_MODE_CONNECTOR_SVIDEO,
2148 &ddc_i2c,
2149 CONNECTOR_OBJECT_ID_SVIDEO,
2150 &hpd);
2151 break;
2152 case CT_MAC_G4_SILVER:
2153 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2154 rdev->mode_info.connector_table);
2155 /* DVI-I - tv dac, int tmds */
2156 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2157 hpd.hpd = RADEON_HPD_1; /* ??? */
2158 radeon_add_legacy_encoder(dev,
2159 radeon_get_encoder_enum(dev,
2160 ATOM_DEVICE_DFP1_SUPPORT,
2161 0),
2162 ATOM_DEVICE_DFP1_SUPPORT);
2163 radeon_add_legacy_encoder(dev,
2164 radeon_get_encoder_enum(dev,
2165 ATOM_DEVICE_CRT2_SUPPORT,
2166 2),
2167 ATOM_DEVICE_CRT2_SUPPORT);
2168 radeon_add_legacy_connector(dev, 0,
2169 ATOM_DEVICE_DFP1_SUPPORT |
2170 ATOM_DEVICE_CRT2_SUPPORT,
2171 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2172 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2173 &hpd);
2174 /* VGA - primary dac */
2175 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2176 hpd.hpd = RADEON_HPD_NONE;
2177 radeon_add_legacy_encoder(dev,
2178 radeon_get_encoder_enum(dev,
2179 ATOM_DEVICE_CRT1_SUPPORT,
2180 1),
2181 ATOM_DEVICE_CRT1_SUPPORT);
2182 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2183 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2184 CONNECTOR_OBJECT_ID_VGA,
2185 &hpd);
2186 /* TV - TV DAC */
2187 ddc_i2c.valid = false;
2188 hpd.hpd = RADEON_HPD_NONE;
2189 radeon_add_legacy_encoder(dev,
2190 radeon_get_encoder_enum(dev,
2191 ATOM_DEVICE_TV1_SUPPORT,
2192 2),
2193 ATOM_DEVICE_TV1_SUPPORT);
2194 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2195 DRM_MODE_CONNECTOR_SVIDEO,
2196 &ddc_i2c,
2197 CONNECTOR_OBJECT_ID_SVIDEO,
2198 &hpd);
2199 break;
2200 default:
2201 DRM_INFO("Connector table: %d (invalid)\n",
2202 rdev->mode_info.connector_table);
2203 return false;
2204 }
2205
2206 radeon_link_encoder_connector(dev);
2207
2208 return true;
2209 }
2210
radeon_apply_legacy_quirks(struct drm_device * dev,int bios_index,enum radeon_combios_connector * legacy_connector,struct radeon_i2c_bus_rec * ddc_i2c,struct radeon_hpd * hpd)2211 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2212 int bios_index,
2213 enum radeon_combios_connector
2214 *legacy_connector,
2215 struct radeon_i2c_bus_rec *ddc_i2c,
2216 struct radeon_hpd *hpd)
2217 {
2218 struct radeon_device *rdev = dev->dev_private;
2219
2220 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2221 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2222 if (rdev->pdev->device == 0x515e &&
2223 rdev->pdev->subsystem_vendor == 0x1014) {
2224 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2225 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2226 return false;
2227 }
2228
2229 /* X300 card with extra non-existent DVI port */
2230 if (rdev->pdev->device == 0x5B60 &&
2231 rdev->pdev->subsystem_vendor == 0x17af &&
2232 rdev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2233 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2234 return false;
2235 }
2236
2237 return true;
2238 }
2239
radeon_apply_legacy_tv_quirks(struct drm_device * dev)2240 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2241 {
2242 struct radeon_device *rdev = dev->dev_private;
2243
2244 /* Acer 5102 has non-existent TV port */
2245 if (rdev->pdev->device == 0x5975 &&
2246 rdev->pdev->subsystem_vendor == 0x1025 &&
2247 rdev->pdev->subsystem_device == 0x009f)
2248 return false;
2249
2250 /* HP dc5750 has non-existent TV port */
2251 if (rdev->pdev->device == 0x5974 &&
2252 rdev->pdev->subsystem_vendor == 0x103c &&
2253 rdev->pdev->subsystem_device == 0x280a)
2254 return false;
2255
2256 /* MSI S270 has non-existent TV port */
2257 if (rdev->pdev->device == 0x5955 &&
2258 rdev->pdev->subsystem_vendor == 0x1462 &&
2259 rdev->pdev->subsystem_device == 0x0131)
2260 return false;
2261
2262 return true;
2263 }
2264
combios_check_dl_dvi(struct drm_device * dev,int is_dvi_d)2265 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2266 {
2267 struct radeon_device *rdev = dev->dev_private;
2268 uint32_t ext_tmds_info;
2269
2270 if (rdev->flags & RADEON_IS_IGP) {
2271 if (is_dvi_d)
2272 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2273 else
2274 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2275 }
2276 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2277 if (ext_tmds_info) {
2278 uint8_t rev = RBIOS8(ext_tmds_info);
2279 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2280 if (rev >= 3) {
2281 if (is_dvi_d)
2282 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2283 else
2284 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2285 } else {
2286 if (flags & 1) {
2287 if (is_dvi_d)
2288 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2289 else
2290 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2291 }
2292 }
2293 }
2294 if (is_dvi_d)
2295 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2296 else
2297 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2298 }
2299
radeon_get_legacy_connector_info_from_bios(struct drm_device * dev)2300 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2301 {
2302 struct radeon_device *rdev = dev->dev_private;
2303 uint32_t conn_info, entry, devices;
2304 uint16_t tmp, connector_object_id;
2305 enum radeon_combios_ddc ddc_type;
2306 enum radeon_combios_connector connector;
2307 int i = 0;
2308 struct radeon_i2c_bus_rec ddc_i2c;
2309 struct radeon_hpd hpd;
2310
2311 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2312 if (conn_info) {
2313 for (i = 0; i < 4; i++) {
2314 entry = conn_info + 2 + i * 2;
2315
2316 if (!RBIOS16(entry))
2317 break;
2318
2319 tmp = RBIOS16(entry);
2320
2321 connector = (tmp >> 12) & 0xf;
2322
2323 ddc_type = (tmp >> 8) & 0xf;
2324 if (ddc_type == 5)
2325 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2326 else
2327 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2328
2329 switch (connector) {
2330 case CONNECTOR_PROPRIETARY_LEGACY:
2331 case CONNECTOR_DVI_I_LEGACY:
2332 case CONNECTOR_DVI_D_LEGACY:
2333 if ((tmp >> 4) & 0x1)
2334 hpd.hpd = RADEON_HPD_2;
2335 else
2336 hpd.hpd = RADEON_HPD_1;
2337 break;
2338 default:
2339 hpd.hpd = RADEON_HPD_NONE;
2340 break;
2341 }
2342
2343 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2344 &ddc_i2c, &hpd))
2345 continue;
2346
2347 switch (connector) {
2348 case CONNECTOR_PROPRIETARY_LEGACY:
2349 if ((tmp >> 4) & 0x1)
2350 devices = ATOM_DEVICE_DFP2_SUPPORT;
2351 else
2352 devices = ATOM_DEVICE_DFP1_SUPPORT;
2353 radeon_add_legacy_encoder(dev,
2354 radeon_get_encoder_enum
2355 (dev, devices, 0),
2356 devices);
2357 radeon_add_legacy_connector(dev, i, devices,
2358 legacy_connector_convert
2359 [connector],
2360 &ddc_i2c,
2361 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2362 &hpd);
2363 break;
2364 case CONNECTOR_CRT_LEGACY:
2365 if (tmp & 0x1) {
2366 devices = ATOM_DEVICE_CRT2_SUPPORT;
2367 radeon_add_legacy_encoder(dev,
2368 radeon_get_encoder_enum
2369 (dev,
2370 ATOM_DEVICE_CRT2_SUPPORT,
2371 2),
2372 ATOM_DEVICE_CRT2_SUPPORT);
2373 } else {
2374 devices = ATOM_DEVICE_CRT1_SUPPORT;
2375 radeon_add_legacy_encoder(dev,
2376 radeon_get_encoder_enum
2377 (dev,
2378 ATOM_DEVICE_CRT1_SUPPORT,
2379 1),
2380 ATOM_DEVICE_CRT1_SUPPORT);
2381 }
2382 radeon_add_legacy_connector(dev,
2383 i,
2384 devices,
2385 legacy_connector_convert
2386 [connector],
2387 &ddc_i2c,
2388 CONNECTOR_OBJECT_ID_VGA,
2389 &hpd);
2390 break;
2391 case CONNECTOR_DVI_I_LEGACY:
2392 devices = 0;
2393 if (tmp & 0x1) {
2394 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2395 radeon_add_legacy_encoder(dev,
2396 radeon_get_encoder_enum
2397 (dev,
2398 ATOM_DEVICE_CRT2_SUPPORT,
2399 2),
2400 ATOM_DEVICE_CRT2_SUPPORT);
2401 } else {
2402 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2403 radeon_add_legacy_encoder(dev,
2404 radeon_get_encoder_enum
2405 (dev,
2406 ATOM_DEVICE_CRT1_SUPPORT,
2407 1),
2408 ATOM_DEVICE_CRT1_SUPPORT);
2409 }
2410 /* RV100 board with external TDMS bit mis-set.
2411 * Actually uses internal TMDS, clear the bit.
2412 */
2413 if (rdev->pdev->device == 0x5159 &&
2414 rdev->pdev->subsystem_vendor == 0x1014 &&
2415 rdev->pdev->subsystem_device == 0x029A) {
2416 tmp &= ~(1 << 4);
2417 }
2418 if ((tmp >> 4) & 0x1) {
2419 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2420 radeon_add_legacy_encoder(dev,
2421 radeon_get_encoder_enum
2422 (dev,
2423 ATOM_DEVICE_DFP2_SUPPORT,
2424 0),
2425 ATOM_DEVICE_DFP2_SUPPORT);
2426 connector_object_id = combios_check_dl_dvi(dev, 0);
2427 } else {
2428 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2429 radeon_add_legacy_encoder(dev,
2430 radeon_get_encoder_enum
2431 (dev,
2432 ATOM_DEVICE_DFP1_SUPPORT,
2433 0),
2434 ATOM_DEVICE_DFP1_SUPPORT);
2435 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2436 }
2437 radeon_add_legacy_connector(dev,
2438 i,
2439 devices,
2440 legacy_connector_convert
2441 [connector],
2442 &ddc_i2c,
2443 connector_object_id,
2444 &hpd);
2445 break;
2446 case CONNECTOR_DVI_D_LEGACY:
2447 if ((tmp >> 4) & 0x1) {
2448 devices = ATOM_DEVICE_DFP2_SUPPORT;
2449 connector_object_id = combios_check_dl_dvi(dev, 1);
2450 } else {
2451 devices = ATOM_DEVICE_DFP1_SUPPORT;
2452 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2453 }
2454 radeon_add_legacy_encoder(dev,
2455 radeon_get_encoder_enum
2456 (dev, devices, 0),
2457 devices);
2458 radeon_add_legacy_connector(dev, i, devices,
2459 legacy_connector_convert
2460 [connector],
2461 &ddc_i2c,
2462 connector_object_id,
2463 &hpd);
2464 break;
2465 case CONNECTOR_CTV_LEGACY:
2466 case CONNECTOR_STV_LEGACY:
2467 radeon_add_legacy_encoder(dev,
2468 radeon_get_encoder_enum
2469 (dev,
2470 ATOM_DEVICE_TV1_SUPPORT,
2471 2),
2472 ATOM_DEVICE_TV1_SUPPORT);
2473 radeon_add_legacy_connector(dev, i,
2474 ATOM_DEVICE_TV1_SUPPORT,
2475 legacy_connector_convert
2476 [connector],
2477 &ddc_i2c,
2478 CONNECTOR_OBJECT_ID_SVIDEO,
2479 &hpd);
2480 break;
2481 default:
2482 DRM_ERROR("Unknown connector type: %d\n",
2483 connector);
2484 continue;
2485 }
2486
2487 }
2488 } else {
2489 uint16_t tmds_info =
2490 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2491 if (tmds_info) {
2492 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2493
2494 radeon_add_legacy_encoder(dev,
2495 radeon_get_encoder_enum(dev,
2496 ATOM_DEVICE_CRT1_SUPPORT,
2497 1),
2498 ATOM_DEVICE_CRT1_SUPPORT);
2499 radeon_add_legacy_encoder(dev,
2500 radeon_get_encoder_enum(dev,
2501 ATOM_DEVICE_DFP1_SUPPORT,
2502 0),
2503 ATOM_DEVICE_DFP1_SUPPORT);
2504
2505 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2506 hpd.hpd = RADEON_HPD_1;
2507 radeon_add_legacy_connector(dev,
2508 0,
2509 ATOM_DEVICE_CRT1_SUPPORT |
2510 ATOM_DEVICE_DFP1_SUPPORT,
2511 DRM_MODE_CONNECTOR_DVII,
2512 &ddc_i2c,
2513 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2514 &hpd);
2515 } else {
2516 uint16_t crt_info =
2517 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2518 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2519 if (crt_info) {
2520 radeon_add_legacy_encoder(dev,
2521 radeon_get_encoder_enum(dev,
2522 ATOM_DEVICE_CRT1_SUPPORT,
2523 1),
2524 ATOM_DEVICE_CRT1_SUPPORT);
2525 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2526 hpd.hpd = RADEON_HPD_NONE;
2527 radeon_add_legacy_connector(dev,
2528 0,
2529 ATOM_DEVICE_CRT1_SUPPORT,
2530 DRM_MODE_CONNECTOR_VGA,
2531 &ddc_i2c,
2532 CONNECTOR_OBJECT_ID_VGA,
2533 &hpd);
2534 } else {
2535 DRM_DEBUG_KMS("No connector info found\n");
2536 return false;
2537 }
2538 }
2539 }
2540
2541 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2542 uint16_t lcd_info =
2543 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2544 if (lcd_info) {
2545 uint16_t lcd_ddc_info =
2546 combios_get_table_offset(dev,
2547 COMBIOS_LCD_DDC_INFO_TABLE);
2548
2549 radeon_add_legacy_encoder(dev,
2550 radeon_get_encoder_enum(dev,
2551 ATOM_DEVICE_LCD1_SUPPORT,
2552 0),
2553 ATOM_DEVICE_LCD1_SUPPORT);
2554
2555 if (lcd_ddc_info) {
2556 ddc_type = RBIOS8(lcd_ddc_info + 2);
2557 switch (ddc_type) {
2558 case DDC_LCD:
2559 ddc_i2c =
2560 combios_setup_i2c_bus(rdev,
2561 DDC_LCD,
2562 RBIOS32(lcd_ddc_info + 3),
2563 RBIOS32(lcd_ddc_info + 7));
2564 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2565 break;
2566 case DDC_GPIO:
2567 ddc_i2c =
2568 combios_setup_i2c_bus(rdev,
2569 DDC_GPIO,
2570 RBIOS32(lcd_ddc_info + 3),
2571 RBIOS32(lcd_ddc_info + 7));
2572 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2573 break;
2574 default:
2575 ddc_i2c =
2576 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2577 break;
2578 }
2579 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2580 } else
2581 ddc_i2c.valid = false;
2582
2583 hpd.hpd = RADEON_HPD_NONE;
2584 radeon_add_legacy_connector(dev,
2585 5,
2586 ATOM_DEVICE_LCD1_SUPPORT,
2587 DRM_MODE_CONNECTOR_LVDS,
2588 &ddc_i2c,
2589 CONNECTOR_OBJECT_ID_LVDS,
2590 &hpd);
2591 }
2592 }
2593
2594 /* check TV table */
2595 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2596 uint32_t tv_info =
2597 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2598 if (tv_info) {
2599 if (RBIOS8(tv_info + 6) == 'T') {
2600 if (radeon_apply_legacy_tv_quirks(dev)) {
2601 hpd.hpd = RADEON_HPD_NONE;
2602 ddc_i2c.valid = false;
2603 radeon_add_legacy_encoder(dev,
2604 radeon_get_encoder_enum
2605 (dev,
2606 ATOM_DEVICE_TV1_SUPPORT,
2607 2),
2608 ATOM_DEVICE_TV1_SUPPORT);
2609 radeon_add_legacy_connector(dev, 6,
2610 ATOM_DEVICE_TV1_SUPPORT,
2611 DRM_MODE_CONNECTOR_SVIDEO,
2612 &ddc_i2c,
2613 CONNECTOR_OBJECT_ID_SVIDEO,
2614 &hpd);
2615 }
2616 }
2617 }
2618 }
2619
2620 radeon_link_encoder_connector(dev);
2621
2622 return true;
2623 }
2624
2625 static const char *thermal_controller_names[] = {
2626 "NONE",
2627 "lm63",
2628 "adm1032",
2629 };
2630
radeon_combios_get_power_modes(struct radeon_device * rdev)2631 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2632 {
2633 struct drm_device *dev = rdev_to_drm(rdev);
2634 u16 offset, misc, misc2 = 0;
2635 u8 rev, tmp;
2636 int state_index = 0;
2637 struct radeon_i2c_bus_rec i2c_bus;
2638
2639 rdev->pm.default_power_state_index = -1;
2640
2641 /* allocate 2 power states */
2642 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state),
2643 GFP_KERNEL);
2644 if (rdev->pm.power_state) {
2645 /* allocate 1 clock mode per state */
2646 rdev->pm.power_state[0].clock_info =
2647 kcalloc(1, sizeof(struct radeon_pm_clock_info),
2648 GFP_KERNEL);
2649 rdev->pm.power_state[1].clock_info =
2650 kcalloc(1, sizeof(struct radeon_pm_clock_info),
2651 GFP_KERNEL);
2652 if (!rdev->pm.power_state[0].clock_info ||
2653 !rdev->pm.power_state[1].clock_info)
2654 goto pm_failed;
2655 } else
2656 goto pm_failed;
2657
2658 /* check for a thermal chip */
2659 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2660 if (offset) {
2661 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2662
2663 rev = RBIOS8(offset);
2664
2665 if (rev == 0) {
2666 thermal_controller = RBIOS8(offset + 3);
2667 gpio = RBIOS8(offset + 4) & 0x3f;
2668 i2c_addr = RBIOS8(offset + 5);
2669 } else if (rev == 1) {
2670 thermal_controller = RBIOS8(offset + 4);
2671 gpio = RBIOS8(offset + 5) & 0x3f;
2672 i2c_addr = RBIOS8(offset + 6);
2673 } else if (rev == 2) {
2674 thermal_controller = RBIOS8(offset + 4);
2675 gpio = RBIOS8(offset + 5) & 0x3f;
2676 i2c_addr = RBIOS8(offset + 6);
2677 clk_bit = RBIOS8(offset + 0xa);
2678 data_bit = RBIOS8(offset + 0xb);
2679 }
2680 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2681 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2682 thermal_controller_names[thermal_controller],
2683 i2c_addr >> 1);
2684 if (gpio == DDC_LCD) {
2685 /* MM i2c */
2686 i2c_bus.valid = true;
2687 i2c_bus.hw_capable = true;
2688 i2c_bus.mm_i2c = true;
2689 i2c_bus.i2c_id = 0xa0;
2690 } else if (gpio == DDC_GPIO)
2691 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2692 else
2693 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2694 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2695 #ifdef notyet
2696 if (rdev->pm.i2c_bus) {
2697 struct i2c_board_info info = { };
2698 const char *name = thermal_controller_names[thermal_controller];
2699 info.addr = i2c_addr >> 1;
2700 strscpy(info.type, name, sizeof(info.type));
2701 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2702 }
2703 #endif
2704 }
2705 } else {
2706 /* boards with a thermal chip, but no overdrive table */
2707
2708 /* Asus 9600xt has an f75375 on the monid bus */
2709 if ((rdev->pdev->device == 0x4152) &&
2710 (rdev->pdev->subsystem_vendor == 0x1043) &&
2711 (rdev->pdev->subsystem_device == 0xc002)) {
2712 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2713 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2714 #ifdef notyet
2715 if (rdev->pm.i2c_bus) {
2716 struct i2c_board_info info = { };
2717 const char *name = "f75375";
2718 info.addr = 0x28;
2719 strscpy(info.type, name, sizeof(info.type));
2720 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2721 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2722 name, info.addr);
2723 }
2724 #endif
2725 }
2726 }
2727
2728 if (rdev->flags & RADEON_IS_MOBILITY) {
2729 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2730 if (offset) {
2731 rev = RBIOS8(offset);
2732 /* power mode 0 tends to be the only valid one */
2733 rdev->pm.power_state[state_index].num_clock_modes = 1;
2734 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2735 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2736 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2737 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2738 goto default_mode;
2739 rdev->pm.power_state[state_index].type =
2740 POWER_STATE_TYPE_BATTERY;
2741 misc = RBIOS16(offset + 0x5 + 0x0);
2742 if (rev > 4)
2743 misc2 = RBIOS16(offset + 0x5 + 0xe);
2744 rdev->pm.power_state[state_index].misc = misc;
2745 rdev->pm.power_state[state_index].misc2 = misc2;
2746 if (misc & 0x4) {
2747 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2748 if (misc & 0x8)
2749 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2750 true;
2751 else
2752 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2753 false;
2754 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2755 if (rev < 6) {
2756 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2757 RBIOS16(offset + 0x5 + 0xb) * 4;
2758 tmp = RBIOS8(offset + 0x5 + 0xd);
2759 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2760 } else {
2761 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2762 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2763 if (entries && voltage_table_offset) {
2764 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2765 RBIOS16(voltage_table_offset) * 4;
2766 tmp = RBIOS8(voltage_table_offset + 0x2);
2767 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2768 } else
2769 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2770 }
2771 switch ((misc2 & 0x700) >> 8) {
2772 case 0:
2773 default:
2774 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2775 break;
2776 case 1:
2777 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2778 break;
2779 case 2:
2780 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2781 break;
2782 case 3:
2783 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2784 break;
2785 case 4:
2786 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2787 break;
2788 }
2789 } else
2790 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2791 if (rev > 6)
2792 rdev->pm.power_state[state_index].pcie_lanes =
2793 RBIOS8(offset + 0x5 + 0x10);
2794 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2795 state_index++;
2796 } else {
2797 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2798 }
2799 } else {
2800 /* XXX figure out some good default low power mode for desktop cards */
2801 }
2802
2803 default_mode:
2804 /* add the default mode */
2805 rdev->pm.power_state[state_index].type =
2806 POWER_STATE_TYPE_DEFAULT;
2807 rdev->pm.power_state[state_index].num_clock_modes = 1;
2808 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2809 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2810 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2811 if ((state_index > 0) &&
2812 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2813 rdev->pm.power_state[state_index].clock_info[0].voltage =
2814 rdev->pm.power_state[0].clock_info[0].voltage;
2815 else
2816 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2817 rdev->pm.power_state[state_index].pcie_lanes = 16;
2818 rdev->pm.power_state[state_index].flags = 0;
2819 rdev->pm.default_power_state_index = state_index;
2820 rdev->pm.num_power_states = state_index + 1;
2821
2822 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2823 rdev->pm.current_clock_mode_index = 0;
2824 return;
2825
2826 pm_failed:
2827 rdev->pm.default_power_state_index = state_index;
2828 rdev->pm.num_power_states = 0;
2829
2830 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2831 rdev->pm.current_clock_mode_index = 0;
2832 }
2833
radeon_external_tmds_setup(struct drm_encoder * encoder)2834 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2835 {
2836 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2837 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2838
2839 if (!tmds)
2840 return;
2841
2842 switch (tmds->dvo_chip) {
2843 case DVO_SIL164:
2844 /* sil 164 */
2845 radeon_i2c_put_byte(tmds->i2c_bus,
2846 tmds->slave_addr,
2847 0x08, 0x30);
2848 radeon_i2c_put_byte(tmds->i2c_bus,
2849 tmds->slave_addr,
2850 0x09, 0x00);
2851 radeon_i2c_put_byte(tmds->i2c_bus,
2852 tmds->slave_addr,
2853 0x0a, 0x90);
2854 radeon_i2c_put_byte(tmds->i2c_bus,
2855 tmds->slave_addr,
2856 0x0c, 0x89);
2857 radeon_i2c_put_byte(tmds->i2c_bus,
2858 tmds->slave_addr,
2859 0x08, 0x3b);
2860 break;
2861 case DVO_SIL1178:
2862 /* sil 1178 - untested */
2863 /*
2864 * 0x0f, 0x44
2865 * 0x0f, 0x4c
2866 * 0x0e, 0x01
2867 * 0x0a, 0x80
2868 * 0x09, 0x30
2869 * 0x0c, 0xc9
2870 * 0x0d, 0x70
2871 * 0x08, 0x32
2872 * 0x08, 0x33
2873 */
2874 break;
2875 default:
2876 break;
2877 }
2878
2879 }
2880
radeon_combios_external_tmds_setup(struct drm_encoder * encoder)2881 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2882 {
2883 struct drm_device *dev = encoder->dev;
2884 struct radeon_device *rdev = dev->dev_private;
2885 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2886 uint16_t offset;
2887 uint8_t blocks, slave_addr, rev;
2888 uint32_t index, id;
2889 uint32_t reg, val, and_mask, or_mask;
2890 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2891
2892 if (!tmds)
2893 return false;
2894
2895 if (rdev->flags & RADEON_IS_IGP) {
2896 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2897 rev = RBIOS8(offset);
2898 if (offset) {
2899 rev = RBIOS8(offset);
2900 if (rev > 1) {
2901 blocks = RBIOS8(offset + 3);
2902 index = offset + 4;
2903 while (blocks > 0) {
2904 id = RBIOS16(index);
2905 index += 2;
2906 switch (id >> 13) {
2907 case 0:
2908 reg = (id & 0x1fff) * 4;
2909 val = RBIOS32(index);
2910 index += 4;
2911 WREG32(reg, val);
2912 break;
2913 case 2:
2914 reg = (id & 0x1fff) * 4;
2915 and_mask = RBIOS32(index);
2916 index += 4;
2917 or_mask = RBIOS32(index);
2918 index += 4;
2919 val = RREG32(reg);
2920 val = (val & and_mask) | or_mask;
2921 WREG32(reg, val);
2922 break;
2923 case 3:
2924 val = RBIOS16(index);
2925 index += 2;
2926 udelay(val);
2927 break;
2928 case 4:
2929 val = RBIOS16(index);
2930 index += 2;
2931 mdelay(val);
2932 break;
2933 case 6:
2934 slave_addr = id & 0xff;
2935 slave_addr >>= 1; /* 7 bit addressing */
2936 index++;
2937 reg = RBIOS8(index);
2938 index++;
2939 val = RBIOS8(index);
2940 index++;
2941 radeon_i2c_put_byte(tmds->i2c_bus,
2942 slave_addr,
2943 reg, val);
2944 break;
2945 default:
2946 DRM_ERROR("Unknown id %d\n", id >> 13);
2947 break;
2948 }
2949 blocks--;
2950 }
2951 return true;
2952 }
2953 }
2954 } else {
2955 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2956 if (offset) {
2957 index = offset + 10;
2958 id = RBIOS16(index);
2959 while (id != 0xffff) {
2960 index += 2;
2961 switch (id >> 13) {
2962 case 0:
2963 reg = (id & 0x1fff) * 4;
2964 val = RBIOS32(index);
2965 WREG32(reg, val);
2966 break;
2967 case 2:
2968 reg = (id & 0x1fff) * 4;
2969 and_mask = RBIOS32(index);
2970 index += 4;
2971 or_mask = RBIOS32(index);
2972 index += 4;
2973 val = RREG32(reg);
2974 val = (val & and_mask) | or_mask;
2975 WREG32(reg, val);
2976 break;
2977 case 4:
2978 val = RBIOS16(index);
2979 index += 2;
2980 udelay(val);
2981 break;
2982 case 5:
2983 reg = id & 0x1fff;
2984 and_mask = RBIOS32(index);
2985 index += 4;
2986 or_mask = RBIOS32(index);
2987 index += 4;
2988 val = RREG32_PLL(reg);
2989 val = (val & and_mask) | or_mask;
2990 WREG32_PLL(reg, val);
2991 break;
2992 case 6:
2993 reg = id & 0x1fff;
2994 val = RBIOS8(index);
2995 index += 1;
2996 radeon_i2c_put_byte(tmds->i2c_bus,
2997 tmds->slave_addr,
2998 reg, val);
2999 break;
3000 default:
3001 DRM_ERROR("Unknown id %d\n", id >> 13);
3002 break;
3003 }
3004 id = RBIOS16(index);
3005 }
3006 return true;
3007 }
3008 }
3009 return false;
3010 }
3011
combios_parse_mmio_table(struct drm_device * dev,uint16_t offset)3012 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3013 {
3014 struct radeon_device *rdev = dev->dev_private;
3015
3016 if (offset) {
3017 while (RBIOS16(offset)) {
3018 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3019 uint32_t addr = (RBIOS16(offset) & 0x1fff);
3020 uint32_t val, and_mask, or_mask;
3021 uint32_t tmp;
3022
3023 offset += 2;
3024 switch (cmd) {
3025 case 0:
3026 val = RBIOS32(offset);
3027 offset += 4;
3028 WREG32(addr, val);
3029 break;
3030 case 1:
3031 val = RBIOS32(offset);
3032 offset += 4;
3033 WREG32(addr, val);
3034 break;
3035 case 2:
3036 and_mask = RBIOS32(offset);
3037 offset += 4;
3038 or_mask = RBIOS32(offset);
3039 offset += 4;
3040 tmp = RREG32(addr);
3041 tmp &= and_mask;
3042 tmp |= or_mask;
3043 WREG32(addr, tmp);
3044 break;
3045 case 3:
3046 and_mask = RBIOS32(offset);
3047 offset += 4;
3048 or_mask = RBIOS32(offset);
3049 offset += 4;
3050 tmp = RREG32(addr);
3051 tmp &= and_mask;
3052 tmp |= or_mask;
3053 WREG32(addr, tmp);
3054 break;
3055 case 4:
3056 val = RBIOS16(offset);
3057 offset += 2;
3058 udelay(val);
3059 break;
3060 case 5:
3061 val = RBIOS16(offset);
3062 offset += 2;
3063 switch (addr) {
3064 case 8:
3065 while (val--) {
3066 if (!
3067 (RREG32_PLL
3068 (RADEON_CLK_PWRMGT_CNTL) &
3069 RADEON_MC_BUSY))
3070 break;
3071 }
3072 break;
3073 case 9:
3074 while (val--) {
3075 if ((RREG32(RADEON_MC_STATUS) &
3076 RADEON_MC_IDLE))
3077 break;
3078 }
3079 break;
3080 default:
3081 break;
3082 }
3083 break;
3084 default:
3085 break;
3086 }
3087 }
3088 }
3089 }
3090
combios_parse_pll_table(struct drm_device * dev,uint16_t offset)3091 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3092 {
3093 struct radeon_device *rdev = dev->dev_private;
3094
3095 if (offset) {
3096 while (RBIOS8(offset)) {
3097 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3098 uint8_t addr = (RBIOS8(offset) & 0x3f);
3099 uint32_t val, shift, tmp;
3100 uint32_t and_mask, or_mask;
3101
3102 offset++;
3103 switch (cmd) {
3104 case 0:
3105 val = RBIOS32(offset);
3106 offset += 4;
3107 WREG32_PLL(addr, val);
3108 break;
3109 case 1:
3110 shift = RBIOS8(offset) * 8;
3111 offset++;
3112 and_mask = RBIOS8(offset) << shift;
3113 and_mask |= ~(0xff << shift);
3114 offset++;
3115 or_mask = RBIOS8(offset) << shift;
3116 offset++;
3117 tmp = RREG32_PLL(addr);
3118 tmp &= and_mask;
3119 tmp |= or_mask;
3120 WREG32_PLL(addr, tmp);
3121 break;
3122 case 2:
3123 case 3:
3124 tmp = 1000;
3125 switch (addr) {
3126 case 1:
3127 udelay(150);
3128 break;
3129 case 2:
3130 mdelay(1);
3131 break;
3132 case 3:
3133 while (tmp--) {
3134 if (!
3135 (RREG32_PLL
3136 (RADEON_CLK_PWRMGT_CNTL) &
3137 RADEON_MC_BUSY))
3138 break;
3139 }
3140 break;
3141 case 4:
3142 while (tmp--) {
3143 if (RREG32_PLL
3144 (RADEON_CLK_PWRMGT_CNTL) &
3145 RADEON_DLL_READY)
3146 break;
3147 }
3148 break;
3149 case 5:
3150 tmp =
3151 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3152 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3153 #if 0
3154 uint32_t mclk_cntl =
3155 RREG32_PLL
3156 (RADEON_MCLK_CNTL);
3157 mclk_cntl &= 0xffff0000;
3158 /*mclk_cntl |= 0x00001111;*//* ??? */
3159 WREG32_PLL(RADEON_MCLK_CNTL,
3160 mclk_cntl);
3161 mdelay(10);
3162 #endif
3163 WREG32_PLL
3164 (RADEON_CLK_PWRMGT_CNTL,
3165 tmp &
3166 ~RADEON_CG_NO1_DEBUG_0);
3167 mdelay(10);
3168 }
3169 break;
3170 default:
3171 break;
3172 }
3173 break;
3174 default:
3175 break;
3176 }
3177 }
3178 }
3179 }
3180
combios_parse_ram_reset_table(struct drm_device * dev,uint16_t offset)3181 static void combios_parse_ram_reset_table(struct drm_device *dev,
3182 uint16_t offset)
3183 {
3184 struct radeon_device *rdev = dev->dev_private;
3185 uint32_t tmp;
3186
3187 if (offset) {
3188 uint8_t val = RBIOS8(offset);
3189 while (val != 0xff) {
3190 offset++;
3191
3192 if (val == 0x0f) {
3193 uint32_t channel_complete_mask;
3194
3195 if (ASIC_IS_R300(rdev))
3196 channel_complete_mask =
3197 R300_MEM_PWRUP_COMPLETE;
3198 else
3199 channel_complete_mask =
3200 RADEON_MEM_PWRUP_COMPLETE;
3201 tmp = 20000;
3202 while (tmp--) {
3203 if ((RREG32(RADEON_MEM_STR_CNTL) &
3204 channel_complete_mask) ==
3205 channel_complete_mask)
3206 break;
3207 }
3208 } else {
3209 uint32_t or_mask = RBIOS16(offset);
3210 offset += 2;
3211
3212 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3213 tmp &= RADEON_SDRAM_MODE_MASK;
3214 tmp |= or_mask;
3215 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3216
3217 or_mask = val << 24;
3218 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3219 tmp &= RADEON_B3MEM_RESET_MASK;
3220 tmp |= or_mask;
3221 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3222 }
3223 val = RBIOS8(offset);
3224 }
3225 }
3226 }
3227
combios_detect_ram(struct drm_device * dev,int ram,int mem_addr_mapping)3228 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3229 int mem_addr_mapping)
3230 {
3231 struct radeon_device *rdev = dev->dev_private;
3232 uint32_t mem_cntl;
3233 uint32_t mem_size;
3234 uint32_t addr = 0;
3235
3236 mem_cntl = RREG32(RADEON_MEM_CNTL);
3237 if (mem_cntl & RV100_HALF_MODE)
3238 ram /= 2;
3239 mem_size = ram;
3240 mem_cntl &= ~(0xff << 8);
3241 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3242 WREG32(RADEON_MEM_CNTL, mem_cntl);
3243 RREG32(RADEON_MEM_CNTL);
3244
3245 /* sdram reset ? */
3246
3247 /* something like this???? */
3248 while (ram--) {
3249 addr = ram * 1024 * 1024;
3250 /* write to each page */
3251 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3252 /* read back and verify */
3253 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3254 return 0;
3255 }
3256
3257 return mem_size;
3258 }
3259
combios_write_ram_size(struct drm_device * dev)3260 static void combios_write_ram_size(struct drm_device *dev)
3261 {
3262 struct radeon_device *rdev = dev->dev_private;
3263 uint8_t rev;
3264 uint16_t offset;
3265 uint32_t mem_size = 0;
3266 uint32_t mem_cntl = 0;
3267
3268 /* should do something smarter here I guess... */
3269 if (rdev->flags & RADEON_IS_IGP)
3270 return;
3271
3272 /* first check detected mem table */
3273 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3274 if (offset) {
3275 rev = RBIOS8(offset);
3276 if (rev < 3) {
3277 mem_cntl = RBIOS32(offset + 1);
3278 mem_size = RBIOS16(offset + 5);
3279 if ((rdev->family < CHIP_R200) &&
3280 !ASIC_IS_RN50(rdev))
3281 WREG32(RADEON_MEM_CNTL, mem_cntl);
3282 }
3283 }
3284
3285 if (!mem_size) {
3286 offset =
3287 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3288 if (offset) {
3289 rev = RBIOS8(offset - 1);
3290 if (rev < 1) {
3291 if ((rdev->family < CHIP_R200)
3292 && !ASIC_IS_RN50(rdev)) {
3293 int ram = 0;
3294 int mem_addr_mapping = 0;
3295
3296 while (RBIOS8(offset)) {
3297 ram = RBIOS8(offset);
3298 mem_addr_mapping =
3299 RBIOS8(offset + 1);
3300 if (mem_addr_mapping != 0x25)
3301 ram *= 2;
3302 mem_size =
3303 combios_detect_ram(dev, ram,
3304 mem_addr_mapping);
3305 if (mem_size)
3306 break;
3307 offset += 2;
3308 }
3309 } else
3310 mem_size = RBIOS8(offset);
3311 } else {
3312 mem_size = RBIOS8(offset);
3313 mem_size *= 2; /* convert to MB */
3314 }
3315 }
3316 }
3317
3318 mem_size *= (1024 * 1024); /* convert to bytes */
3319 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3320 }
3321
radeon_combios_asic_init(struct drm_device * dev)3322 void radeon_combios_asic_init(struct drm_device *dev)
3323 {
3324 struct radeon_device *rdev = dev->dev_private;
3325 uint16_t table;
3326
3327 /* port hardcoded mac stuff from radeonfb */
3328 if (rdev->bios == NULL)
3329 return;
3330
3331 /* ASIC INIT 1 */
3332 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3333 if (table)
3334 combios_parse_mmio_table(dev, table);
3335
3336 /* PLL INIT */
3337 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3338 if (table)
3339 combios_parse_pll_table(dev, table);
3340
3341 /* ASIC INIT 2 */
3342 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3343 if (table)
3344 combios_parse_mmio_table(dev, table);
3345
3346 if (!(rdev->flags & RADEON_IS_IGP)) {
3347 /* ASIC INIT 4 */
3348 table =
3349 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3350 if (table)
3351 combios_parse_mmio_table(dev, table);
3352
3353 /* RAM RESET */
3354 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3355 if (table)
3356 combios_parse_ram_reset_table(dev, table);
3357
3358 /* ASIC INIT 3 */
3359 table =
3360 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3361 if (table)
3362 combios_parse_mmio_table(dev, table);
3363
3364 /* write CONFIG_MEMSIZE */
3365 combios_write_ram_size(dev);
3366 }
3367
3368 /* quirk for rs4xx HP nx6125 laptop to make it resume
3369 * - it hangs on resume inside the dynclk 1 table.
3370 */
3371 if (rdev->family == CHIP_RS480 &&
3372 rdev->pdev->subsystem_vendor == 0x103c &&
3373 rdev->pdev->subsystem_device == 0x308b)
3374 return;
3375
3376 /* quirk for rs4xx HP dv5000 laptop to make it resume
3377 * - it hangs on resume inside the dynclk 1 table.
3378 */
3379 if (rdev->family == CHIP_RS480 &&
3380 rdev->pdev->subsystem_vendor == 0x103c &&
3381 rdev->pdev->subsystem_device == 0x30a4)
3382 return;
3383
3384 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3385 * - it hangs on resume inside the dynclk 1 table.
3386 */
3387 if (rdev->family == CHIP_RS480 &&
3388 rdev->pdev->subsystem_vendor == 0x103c &&
3389 rdev->pdev->subsystem_device == 0x30ae)
3390 return;
3391
3392 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3393 * - it hangs on resume inside the dynclk 1 table.
3394 */
3395 if (rdev->family == CHIP_RS480 &&
3396 rdev->pdev->subsystem_vendor == 0x103c &&
3397 rdev->pdev->subsystem_device == 0x280a)
3398 return;
3399 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume
3400 * - it hangs on resume inside the dynclk 1 table.
3401 */
3402 if (rdev->family == CHIP_RS400 &&
3403 rdev->pdev->subsystem_vendor == 0x1179 &&
3404 rdev->pdev->subsystem_device == 0xff31)
3405 return;
3406
3407 /* DYN CLK 1 */
3408 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3409 if (table)
3410 combios_parse_pll_table(dev, table);
3411
3412 }
3413
radeon_combios_initialize_bios_scratch_regs(struct drm_device * dev)3414 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3415 {
3416 struct radeon_device *rdev = dev->dev_private;
3417 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3418
3419 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3420 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3421 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3422
3423 /* let the bios control the backlight */
3424 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3425
3426 /* tell the bios not to handle mode switching */
3427 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3428 RADEON_ACC_MODE_CHANGE);
3429
3430 /* tell the bios a driver is loaded */
3431 bios_7_scratch |= RADEON_DRV_LOADED;
3432
3433 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3434 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3435 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3436 }
3437
radeon_combios_output_lock(struct drm_encoder * encoder,bool lock)3438 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3439 {
3440 struct drm_device *dev = encoder->dev;
3441 struct radeon_device *rdev = dev->dev_private;
3442 uint32_t bios_6_scratch;
3443
3444 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3445
3446 if (lock)
3447 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3448 else
3449 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3450
3451 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3452 }
3453
3454 void
radeon_combios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)3455 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3456 struct drm_encoder *encoder,
3457 bool connected)
3458 {
3459 struct drm_device *dev = connector->dev;
3460 struct radeon_device *rdev = dev->dev_private;
3461 struct radeon_connector *radeon_connector =
3462 to_radeon_connector(connector);
3463 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3464 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3465 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3466
3467 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3468 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3469 if (connected) {
3470 DRM_DEBUG_KMS("TV1 connected\n");
3471 /* fix me */
3472 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3473 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3474 bios_5_scratch |= RADEON_TV1_ON;
3475 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3476 } else {
3477 DRM_DEBUG_KMS("TV1 disconnected\n");
3478 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3479 bios_5_scratch &= ~RADEON_TV1_ON;
3480 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3481 }
3482 }
3483 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3484 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3485 if (connected) {
3486 DRM_DEBUG_KMS("LCD1 connected\n");
3487 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3488 bios_5_scratch |= RADEON_LCD1_ON;
3489 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3490 } else {
3491 DRM_DEBUG_KMS("LCD1 disconnected\n");
3492 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3493 bios_5_scratch &= ~RADEON_LCD1_ON;
3494 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3495 }
3496 }
3497 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3498 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3499 if (connected) {
3500 DRM_DEBUG_KMS("CRT1 connected\n");
3501 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3502 bios_5_scratch |= RADEON_CRT1_ON;
3503 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3504 } else {
3505 DRM_DEBUG_KMS("CRT1 disconnected\n");
3506 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3507 bios_5_scratch &= ~RADEON_CRT1_ON;
3508 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3509 }
3510 }
3511 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3512 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3513 if (connected) {
3514 DRM_DEBUG_KMS("CRT2 connected\n");
3515 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3516 bios_5_scratch |= RADEON_CRT2_ON;
3517 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3518 } else {
3519 DRM_DEBUG_KMS("CRT2 disconnected\n");
3520 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3521 bios_5_scratch &= ~RADEON_CRT2_ON;
3522 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3523 }
3524 }
3525 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3526 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3527 if (connected) {
3528 DRM_DEBUG_KMS("DFP1 connected\n");
3529 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3530 bios_5_scratch |= RADEON_DFP1_ON;
3531 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3532 } else {
3533 DRM_DEBUG_KMS("DFP1 disconnected\n");
3534 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3535 bios_5_scratch &= ~RADEON_DFP1_ON;
3536 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3537 }
3538 }
3539 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3540 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3541 if (connected) {
3542 DRM_DEBUG_KMS("DFP2 connected\n");
3543 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3544 bios_5_scratch |= RADEON_DFP2_ON;
3545 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3546 } else {
3547 DRM_DEBUG_KMS("DFP2 disconnected\n");
3548 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3549 bios_5_scratch &= ~RADEON_DFP2_ON;
3550 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3551 }
3552 }
3553 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3554 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3555 }
3556
3557 void
radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)3558 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3559 {
3560 struct drm_device *dev = encoder->dev;
3561 struct radeon_device *rdev = dev->dev_private;
3562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3563 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3564
3565 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3566 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3567 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3568 }
3569 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3570 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3571 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3572 }
3573 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3574 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3575 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3576 }
3577 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3578 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3579 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3580 }
3581 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3582 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3583 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3584 }
3585 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3586 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3587 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3588 }
3589 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3590 }
3591
3592 void
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)3593 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3594 {
3595 struct drm_device *dev = encoder->dev;
3596 struct radeon_device *rdev = dev->dev_private;
3597 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3598 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3599
3600 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3601 if (on)
3602 bios_6_scratch |= RADEON_TV_DPMS_ON;
3603 else
3604 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3605 }
3606 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3607 if (on)
3608 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3609 else
3610 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3611 }
3612 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3613 if (on)
3614 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3615 else
3616 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3617 }
3618 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3619 if (on)
3620 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3621 else
3622 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3623 }
3624 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3625 }
3626