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Searched refs:BIT_ULL (Results 1 – 25 of 26) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/i915/
Di915_gem_gtt.h41 #define PIN_NOEVICT BIT_ULL(0)
42 #define PIN_NOSEARCH BIT_ULL(1)
43 #define PIN_NONBLOCK BIT_ULL(2)
44 #define PIN_MAPPABLE BIT_ULL(3)
45 #define PIN_ZONE_4G BIT_ULL(4)
46 #define PIN_HIGH BIT_ULL(5)
47 #define PIN_OFFSET_BIAS BIT_ULL(6)
48 #define PIN_OFFSET_FIXED BIT_ULL(7)
49 #define PIN_OFFSET_GUARD BIT_ULL(8)
50 #define PIN_VALIDATE BIT_ULL(9) /* validate placement only, no need to call unpin() */
[all …]
/openbsd/src/sys/dev/pci/drm/i915/gt/
Dintel_gtt.h45 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
46 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
47 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
91 #define MTL_PPGTT_PTE_PAT3 BIT_ULL(62)
92 #define GEN12_PPGTT_PTE_LM BIT_ULL(11)
93 #define GEN12_PPGTT_PTE_PAT2 BIT_ULL(7)
94 #define GEN12_PPGTT_PTE_PAT1 BIT_ULL(4)
95 #define GEN12_PPGTT_PTE_PAT0 BIT_ULL(3)
97 #define GEN12_GGTT_PTE_LM BIT_ULL(1)
98 #define MTL_GGTT_PTE_PAT0 BIT_ULL(52)
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Dselftest_tlb.c67 addr = igt_random_offset(prng, addr, min(ce->vm->total, BIT_ULL(48)), in pte_tlbinv()
320 if (BIT_ULL(bit) < i915_vm_obj_min_alignment(va->vm, va->obj)) in mem_tlbinv()
325 BIT_ULL(bit), in mem_tlbinv()
333 BIT_ULL(bit), in mem_tlbinv()
335 BIT_ULL(len), in mem_tlbinv()
Dintel_lrc_reg.h11 #define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
Dintel_ppgtt.c220 return (size + 2 * (BIT_ULL(shift) - 1)) >> shift; in pd_count()
317 ppgtt->vm.total = BIT_ULL(RUNTIME_INFO(i915)->ppgtt_size); in ppgtt_init()
Dgen8_ppgtt.c310 GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT))); in gen8_ppgtt_clear()
311 GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT))); in gen8_ppgtt_clear()
394 GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT))); in gen8_ppgtt_alloc()
395 GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT))); in gen8_ppgtt_alloc()
Dintel_rc6.c817 overflow_hw = BIT_ULL(40); in intel_rc6_residency_ns()
829 overflow_hw = BIT_ULL(32); in intel_rc6_residency_ns()
Dselftest_timeline.c254 u64 ctx = BIT_ULL(order) + offset; in igt_sync()
267 u64 ctx = BIT_ULL(order) + offset; in igt_sync()
/openbsd/src/sys/dev/pci/
Dif_icevar.h2707 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
2708 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
2710 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
2711 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
2713 (BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
2714 BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
2716 (BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
2717 BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
2719 (BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
2720 BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
[all …]
Dif_icereg.h40 #define BIT_ULL(x) (1ULL << (x)) macro
10782 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
10783 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
10784 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
10785 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
10786 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
10787 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
10788 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
10789 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
10790 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
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Dif_ice.c2340 mask = BIT_ULL(ce_info->width) - 1; in ice_write_qword()
10003 uint64_t pow_result = BIT_ULL(i); in ice_sched_bw_to_rl_profile()
13968 uint64_t type = BIT_ULL(bit); in ice_add_media_types()
13991 uint64_t type = BIT_ULL(bit); in ice_add_media_types()
25505 uint64_t new_data = ICE_READ_8(hw, reg) & (BIT_ULL(40) - 1); in ice_stat_update40()
25526 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; in ice_stat_update40()
25567 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; in ice_stat_update32()
/openbsd/src/sys/dev/pci/drm/i915/selftests/
Di915_gem_gtt.c287 GEM_BUG_ON(count * BIT_ULL(aligned_size) > vm->total); in lowlevel_hole()
288 GEM_BUG_ON(hole_start + count * BIT_ULL(aligned_size) > hole_end); in lowlevel_hole()
296 obj = fake_dma_object(vm->i915, BIT_ULL(size)); in lowlevel_hole()
302 GEM_BUG_ON(obj->base.size != BIT_ULL(size)); in lowlevel_hole()
311 u64 addr = hole_start + order[n] * BIT_ULL(aligned_size); in lowlevel_hole()
314 GEM_BUG_ON(addr + BIT_ULL(aligned_size) > vm->total); in lowlevel_hole()
336 BIT_ULL(size))) in lowlevel_hole()
342 addr, BIT_ULL(size)); in lowlevel_hole()
357 mock_vma_res->node_size = BIT_ULL(aligned_size); in lowlevel_hole()
370 u64 addr = hole_start + order[n] * BIT_ULL(aligned_size); in lowlevel_hole()
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Di915_syncmap.c297 u64 context = BIT_ULL(order); in igt_syncmap_join_above()
346 u64 context = step * BIT_ULL(order); in igt_syncmap_join_below()
363 u64 context = step * BIT_ULL(order); in igt_syncmap_join_below()
385 u64 context = step * BIT_ULL(order); in igt_syncmap_join_below()
469 u64 context = idx * BIT_ULL(order) + idx; in igt_syncmap_compact()
Dintel_memory_region.c449 #define SZ_8G BIT_ULL(33)
/openbsd/src/sys/dev/pci/drm/
Ddrm_color_mgmt.c136 u64 mag = (user_input & ~BIT_ULL(63)) >> (32 - n); in drm_color_ctm_s31_32_to_qm_n()
137 bool negative = !!(user_input & BIT_ULL(63)); in drm_color_ctm_s31_32_to_qm_n()
143 BIT_ULL(n + m - 1) : BIT_ULL(n + m - 1) - 1); in drm_color_ctm_s31_32_to_qm_n()
Ddrm_client_modeset.c387 const u64 mask = BIT_ULL(connector_count) - 1; in drm_client_target_preferred()
404 if (conn_configured & BIT_ULL(i)) in drm_client_target_preferred()
408 conn_configured |= BIT_ULL(i); in drm_client_target_preferred()
477 conn_configured |= BIT_ULL(i); in drm_client_target_preferred()
/openbsd/src/sys/dev/pci/drm/i915/gt/uc/
Dintel_gsc_uc_heci_cmd_submit.h46 #define HOST_SESSION_PXP_SINGLE BIT_ULL(60)
/openbsd/src/sys/dev/pci/drm/include/linux/
Dbitops.h29 #define BIT_ULL(x) (1ULL << (x)) macro
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Damdgpu_ras.h72 #define RAS_EVENT_INVALID_ID (BIT_ULL(63))
73 #define RAS_EVENT_ID_IS_VALID(x) (!((x) & BIT_ULL(63)))
Dumc_v12_0.c573 ecc_err->pa_pfn = BIT_ULL(UMC_V12_0_PA_C4_BIT) >> AMDGPU_GPU_PAGE_SHIFT; in umc_v12_0_update_ecc_status()
/openbsd/src/sys/dev/pci/drm/i915/display/
Dintel_display_power_map.c1663 drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id)); in __set_power_wells()
1664 power_well_ids |= BIT_ULL(id); in __set_power_wells()
Dintel_fbc.c764 return BIT_ULL(28); in intel_fbc_cfb_base_max()
766 return BIT_ULL(32); in intel_fbc_cfb_base_max()
/openbsd/src/sys/dev/pci/drm/i915/gem/selftests/
Di915_gem_client_blt.c344 return (offset & BIT_ULL(bit)) >> (bit - 6); in swizzle_bit()
Di915_gem_mman.c41 return (offset & BIT_ULL(bit)) >> (bit - 6); in swizzle_bit()
/openbsd/src/sys/dev/pci/drm/i915/gem/
Di915_gem_execbuffer.c1692 min_t(u64, BIT_ULL(31), size - copied); in eb_copy_relocations()

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