| /openbsd/src/gnu/llvm/llvm/docs/Proposals/ |
| D | VectorPredication.rst | 15 vector instructions for modern SIMD ISAs such as AVX512, ARM SVE, the RISC-V V
43 - VP legalization (legalize explicit vector length to mask (AVX512), legalize VP
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86Subtarget.h | 54 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 enumerator
209 bool hasAVX512() const { return X86SSELevel >= AVX512; } in hasAVX512()
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| D | X86InstrFormats.td | 253 // Specify AVX512 8-bit compressed displacement encoding based on the vector
348 // The scaling factor for AVX512's compressed displacement is either
352 // Possible values are: 0 (non-AVX512 inst), 1, 2, 4, 8, 16, 32 and 64.
524 // SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512
540 // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512
892 class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
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| D | X86InstrAVX512.td | 1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
9 // This file describes the X86 AVX512 instruction set, defining the
221 def NAME: AVX512<O, F, Outs, Ins,
228 def NAME#k: AVX512<O, F, Outs, MaskingIns,
243 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
408 def NAME: AVX512<O, F, Outs, Ins,
413 def NAME#k: AVX512<O, F, Outs, MaskingIns,
2100 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
2698 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2704 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
[all …]
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| D | X86.td | 122 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512",
216 "Promote selected AES instructions to AVX512/AVX registers",
628 "Prefer AVX512 mask registers over PTEST/MOVMSK">;
823 // Skylake-AVX512
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| D | X86ScheduleZnver4.td | 307 // AVX512 Opmask pipelines
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| /openbsd/src/gnu/llvm/llvm/lib/Analysis/ |
| D | VFABIDemangling.cpp | 39 .Case("e", VFISAKind::AVX512) in tryParseISA()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Analysis/ |
| D | VectorUtils.h | 50 AVX512, // x86 AVX512 enumerator
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| /openbsd/src/gnu/llvm/llvm/docs/GlobalISel/ |
| D | GMIR.rst | 146 more potential banks such as one for the AVX512 Mask Registers.
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| /openbsd/src/gnu/llvm/clang/include/clang/Basic/ |
| D | BuiltinsX86.def | 909 // AVX-VNNI and AVX512-VNNI
1785 // AVX512 fp16 intrinsics
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| /openbsd/src/gnu/llvm/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 2245 AVX512 enumerator
2251 case X86AVXABILevel::AVX512: in getNativeVectorSizeForAVXABI()
12368 ? X86AVXABILevel::AVX512 in getTargetCodeGenInfo()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/IR/ |
| D | IntrinsicsX86.td | 2787 // AVX512
4153 // AVX512 gather/scatter intrinsics that use vXi1 masks.
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| /openbsd/src/gnu/llvm/clang/docs/ |
| D | ReleaseNotes.rst | 968 - Switch ``AVX512-BF16`` intrinsics types from ``short`` to ``__bf16``.
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| D | LanguageExtensions.rst | 786 AVX512-FP16, ``_Float16`` arithmetic is performed using that native support.
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| D | UsersManual.rst | 1777 * ``_Float16`` on X86 targets without ``AVX512-FP16``.
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| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | LangRef.rst | 2290 <isa>:= b | c | d | e -> X86 SSE, AVX, AVX2, AVX512
5113 512-bit vector operand in an AVX512 register, Otherwise, an error.
18292 Some targets, such as AVX512, do not support the %evl parameter in hardware.
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