| /openbsd/src/gnu/llvm/llvm/lib/Target/VE/ |
| D | VVPISelLowering.cpp | 24 SDValue AVL = in splitMaskArithmetic() local 28 SDValue LoA = CDAG.getUnpack(MVT::v256i1, A, PackElem::Lo, AVL); in splitMaskArithmetic() 29 SDValue HiA = CDAG.getUnpack(MVT::v256i1, A, PackElem::Hi, AVL); in splitMaskArithmetic() 30 SDValue LoB = CDAG.getUnpack(MVT::v256i1, B, PackElem::Lo, AVL); in splitMaskArithmetic() 31 SDValue HiB = CDAG.getUnpack(MVT::v256i1, B, PackElem::Hi, AVL); in splitMaskArithmetic() 35 return CDAG.getPack(MVT::v512i1, LoRes, HiRes, AVL); in splitMaskArithmetic() 63 SDValue AVL; in lowerToVVP() local 73 AVL = Op->getOperand(*AVLIdx); in lowerToVVP() 77 if (!AVL) in lowerToVVP() 78 AVL = CDAG.getConstant(OpVecVT.getVectorNumElements(), MVT::i32); in lowerToVVP() [all …]
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| D | VECustomDAG.cpp | 214 bool isLegalAVL(SDValue AVL) { return AVL->getOpcode() == VEISD::LEGALAVL; } in isLegalAVL() argument 396 SDValue AVL = getNodeAVL(Op); in getAnnotatedNodeAVL() local 397 if (!AVL) in getAnnotatedNodeAVL() 399 if (isLegalAVL(AVL)) in getAnnotatedNodeAVL() 400 return {AVL->getOperand(0), true}; in getAnnotatedNodeAVL() 401 return {AVL, false}; in getAnnotatedNodeAVL() 414 auto AVL = getConstant(MaskVT.getVectorNumElements(), MVT::i32); in getConstantMask() local 415 auto Res = getNode(VEISD::VEC_BROADCAST, MaskVT, {TrueVal, AVL}); in getConstantMask() 423 SDValue AVL) const { in getMaskBroadcast() 440 DAG.getNode(VEISD::VEC_BROADCAST, DL, CmpVecTy, {CmpElem, AVL}); in getMaskBroadcast() [all …]
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| D | VECustomDAG.h | 77 bool isLegalAVL(SDValue AVL); 137 SDValue AVL; member 138 VETargetMasks(SDValue Mask = SDValue(), SDValue AVL = SDValue()) 139 : Mask(Mask), AVL(AVL) {} in Mask() 185 SDValue VectorV, SDValue Mask, SDValue AVL, 190 SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const; 191 SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const; 202 SDValue getMaskBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const; 203 SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const; 206 SDValue annotateLegalAVL(SDValue AVL) const; [all …]
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| D | VEISelLowering.cpp | 1848 auto AVL = CDAG.getConstant(NumEls, MVT::i32); in lowerBUILD_VECTOR() local 1849 return CDAG.getBroadcast(ResultVT, ScalarV, AVL); in lowerBUILD_VECTOR()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoVSDPatterns.td | 69 (load_instr GPR:$rs1, m.AVL, m.Log2SEW)>; 72 (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>; 114 vti.LMul, vti.AVL, vti.RegClass>; 117 vti.LMul, vti.AVL, vti.RegClass, 128 vti.LMul, vti.AVL, vti.RegClass, 155 vti.LMul, vti.AVL, vti.RegClass>; 158 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass, 170 fvti.AVL, fvti.Log2SEW)>; 179 (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, 191 (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, [all …]
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| D | RISCVInstrInfoVPseudos.td | 25 def AVL : RegisterOperand<GPRNoX0> { 31 // rd | rs1 | AVL value | Effect on vl 162 def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>; 165 // We can't use X0 register becuase the AVL operands use GPRNoX0. 194 // The pattern fragment which produces the AVL operand, representing the 196 OutPatFrag AVL = VLMax; 303 // The pattern fragment which produces the AVL operand, representing the 306 OutPatFrag AVL = VLMax; 665 (ins GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>, 678 (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>, [all …]
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| D | RISCVInsertVSETVLI.cpp | 1138 unsigned AVL = Info.getAVLImm(); in hasFixedResult() local 1140 unsigned AVLInBits = AVL * SEW; in hasFixedResult()
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| D | RISCVISelDAGToDAG.cpp | 579 uint64_t AVL = C->getZExtValue(); in selectVSETVLI() local 580 if (isUInt<5>(AVL)) { in selectVSETVLI() 581 SDValue VLImm = CurDAG->getTargetConstant(AVL, DL, XLenVT); in selectVSETVLI()
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| D | RISCVISelLowering.cpp | 5500 SDValue AVL = getVLOperand(Op); in lowerVectorIntrinsicScalars() local 5504 if (isa<ConstantSDNode>(AVL)) { in lowerVectorIntrinsicScalars() 5516 uint64_t AVLInt = cast<ConstantSDNode>(AVL)->getZExtValue(); in lowerVectorIntrinsicScalars() 5544 SDValue VL = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, SETVL, AVL, in lowerVectorIntrinsicScalars() 5590 AVL); in lowerVectorIntrinsicScalars() 5594 AVL); in lowerVectorIntrinsicScalars() 5974 static bool hasNonZeroAVL(SDValue AVL) { in hasNonZeroAVL() argument 5975 auto *RegisterAVL = dyn_cast<RegisterSDNode>(AVL); in hasNonZeroAVL() 5976 auto *ImmAVL = dyn_cast<ConstantSDNode>(AVL); in hasNonZeroAVL()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/IR/ |
| D | IntrinsicsRISCV.td | 132 /* AVL */ [LLVMMatchType<0>, 148 /* AVL */ [LLVMMatchType<0>,
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| /openbsd/src/gnu/usr.bin/gcc/gcc/ |
| D | FSFChangeLog | 1865 * c-typeck.c: Collect pending initializers in AVL tree instead of list. 1868 (output_pending_init_elements): Rewritten to exploit AVL order.
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| D | ChangeLog.5 | 12659 Call set_nonincremental_init if necessary. Push RECORD/ARRAY into AVL
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| D | FSFChangeLog.11 | 13798 (mark_seen_cases): If SPARSENESS == 2, exploit AVL order.
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| /openbsd/src/share/misc/ |
| D | airport | 127 AVL:Asheville Regional, North Carolina, USA
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| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | ProgrammersManual.rst | 2176 ImmutableSet is an immutable (functional) set implementation based on an AVL 2381 ImmutableMap is an immutable (functional) map implementation based on an AVL
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