1 /* $NetBSD: rtwnreg.h,v 1.3 2020/04/16 17:18:27 nat Exp $ */ 2 /* $OpenBSD: r92creg.h,v 1.16 2017/09/22 13:41:56 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #ifndef _DEV_IC_RTWNREG_H_ 22 #define _DEV_IC_RTWNREG_H_ 23 24 #define R92C_MAX_CHAINS 2 25 #define R92C_MAX_TX_PWR 0x3f 26 #define R92C_H2C_NBOX 4 27 28 /* 29 * MAC registers. 30 */ 31 /* System Configuration. */ 32 #define R92C_SYS_ISO_CTRL 0x000 33 #define R92C_SYS_FUNC_EN 0x002 34 #define R92C_APS_FSMCO 0x004 35 #define R92C_SYS_CLKR 0x008 36 #define R92C_AFE_MISC 0x010 37 #define R92C_SPS0_CTRL 0x011 38 #define R92C_SYS_SWR_CTRL2 0x014 39 #define R92C_SPS_OCP_CFG 0x018 40 #define R92C_RSV_CTRL 0x01c 41 #define R92C_RF_CTRL 0x01f 42 #define R92C_LDOA15_CTRL 0x020 43 #define R92C_LDOV12D_CTRL 0x021 44 #define R92C_LDOHCI12_CTRL 0x022 45 #define R92C_LPLDO_CTRL 0x023 46 #define R92C_AFE_XTAL_CTRL 0x024 47 #define R92C_AFE_PLL_CTRL 0x028 48 #define R92C_AFE_CTRL3 0x02c 49 #define R92C_EFUSE_CTRL 0x030 50 #define R92C_EFUSE_TEST 0x034 51 #define R92C_PWR_DATA 0x038 52 #define R92C_CAL_TIMER 0x03c 53 #define R92C_ACLK_MON 0x03e 54 #define R92C_GPIO_MUXCFG 0x040 55 #define R92C_GPIO_IO_SEL 0x042 56 #define R92C_MAC_PINMUX_CFG 0x043 57 #define R92C_GPIO_PIN_CTRL 0x044 58 #define R92C_GPIO_INTM 0x048 59 #define R92C_LEDCFG0 0x04c 60 #define R92C_LEDCFG1 0x04d 61 #define R92C_LEDCFG2 0x04e 62 #define R92C_LEDCFG3 0x04f 63 #define R92C_FSIMR 0x050 64 #define R92C_FSISR 0x054 65 #define R92C_HSIMR 0x058 66 #define R92C_HSISR 0x05c 67 #define R92C_PAD_CTRL 0x064 68 #define R92C_AFE_CTRL4 0x078 69 #define R92C_MCUFWDL 0x080 70 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 71 #define R88E_HIMR 0x0b0 72 #define R88E_HISR 0x0b4 73 #define R88E_HIMRE 0x0b8 74 #define R88E_HISRE 0x0bc 75 #define R92C_EFUSE_ACCESS 0x0cf 76 #define R92C_BIST_SCAN 0x0d0 77 #define R92C_BIST_RPT 0x0d4 78 #define R92C_BIST_ROM_RPT 0x0d8 79 #define R92C_USB_SIE_INTF 0x0e0 80 #define R92C_PCIE_MIO_INTF 0x0e4 81 #define R92C_PCIE_MIO_INTD 0x0e8 82 #define R92C_HPON_FSM 0x0ec 83 #define R92C_SYS_CFG 0x0f0 84 /* MAC General Configuration. */ 85 #define R92C_CR 0x100 86 #define R92C_MSR 0x102 87 #define R92C_PBP 0x104 88 #define R92C_TRXDMA_CTRL 0x10c 89 #define R92C_TRXFF_BNDY 0x114 90 #define R92C_TRXFF_STATUS 0x118 91 #define R92C_RXFF_PTR 0x11c 92 #define R92C_HIMR 0x120 93 #define R92C_HISR 0x124 94 #define R92C_HIMRE 0x128 95 #define R92C_HISRE 0x12c 96 #define R92C_CPWM 0x12f 97 #define R92C_FWIMR 0x130 98 #define R92C_FWISR 0x134 99 #define R92C_PKTBUF_DBG_CTRL 0x140 100 #define R92C_PKTBUF_DBG_DATA_L 0x144 101 #define R92C_PKTBUF_DBG_DATA_H 0x148 102 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 103 #define R92C_TCUNIT_BASE 0x164 104 #define R92C_MBIST_START 0x174 105 #define R92C_MBIST_DONE 0x178 106 #define R92C_MBIST_FAIL 0x17c 107 #define R92C_C2HEVT_MSG_NORMAL 0x1a0 108 #define R92C_C2HEVT_MSG_TEST 0x1b8 109 #define R92C_C2HEVT_CLEAR 0x1bf 110 #define R92C_MCUTST_1 0x1c0 111 #define R92C_FMETHR 0x1c8 112 #define R92C_HMETFR 0x1cc 113 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 114 #define R92C_LLT_INIT 0x1e0 115 #define R92C_BB_ACCESS_CTRL 0x1e8 116 #define R92C_BB_ACCESS_DATA 0x1ec 117 #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 118 #define R92E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 119 /* Tx DMA Configuration. */ 120 #define R92C_RQPN 0x200 121 #define R92C_FIFOPAGE 0x204 122 #define R92C_TDECTRL 0x208 123 #define R92C_TXDMA_OFFSET_CHK 0x20c 124 #define R92C_TXDMA_STATUS 0x210 125 #define R92C_RQPN_NPQ 0x214 126 /* Rx DMA Configuration. */ 127 #define R92C_RXDMA_AGG_PG_TH 0x280 128 #define R92C_RXPKT_NUM 0x284 129 #define R92C_RXDMA_STATUS 0x288 130 131 #define R92C_PCIE_CTRL_REG 0x300 132 #define R92C_INT_MIG 0x304 133 #define R92C_BCNQ_DESA 0x308 134 #define R92C_HQ_DESA 0x310 135 #define R92C_MGQ_DESA 0x318 136 #define R92C_VOQ_DESA 0x320 137 #define R92C_VIQ_DESA 0x328 138 #define R92C_BEQ_DESA 0x330 139 #define R92C_BKQ_DESA 0x338 140 #define R92C_RX_DESA 0x340 141 #define R92C_DBI 0x348 142 #define R92C_MDIO 0x354 143 #define R92C_DBG_SEL 0x360 144 #define R92C_PCIE_HRPWM 0x361 145 #define R92C_PCIE_HCPWM 0x363 146 #define R92C_UART_CTRL 0x364 147 #define R92C_UART_TX_DES 0x370 148 #define R92C_UART_RX_DES 0x378 149 150 #define R92C_VOQ_INFORMATION 0x0400 151 #define R92C_VIQ_INFORMATION 0x0404 152 #define R92C_BEQ_INFORMATION 0x0408 153 #define R92C_BKQ_INFORMATION 0x040C 154 #define R92C_MGQ_INFORMATION 0x0410 155 #define R92C_HGQ_INFORMATION 0x0414 156 #define R92C_BCNQ_INFORMATION 0x0418 157 #define R92C_CPU_MGQ_INFORMATION 0x041C 158 159 /* Protocol Configuration. */ 160 #define R92C_FWHW_TXQ_CTRL 0x420 161 #define R92C_HWSEQ_CTRL 0x423 162 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 163 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 164 #define R92C_SPEC_SIFS 0x428 165 #define R92C_RL 0x42a 166 #define R92C_DARFRC 0x430 167 #define R92C_RARFRC 0x438 168 #define R92C_RRSR 0x440 169 #define R92C_ARFR(i) (0x444 + (i) * 4) 170 #define R92C_AGGLEN_LMT 0x458 171 #define R92C_AMPDU_MIN_SPACE 0x45c 172 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 173 #define R92C_FAST_EDCA_CTRL 0x460 174 #define R92C_RD_RESP_PKT_TH 0x463 175 #define R92C_INIRTS_RATE_SEL 0x480 176 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 177 #define R92C_MAX_AGGR_NUM 0x4ca 178 #define R92C_PROT_MODE_CTRL 0x4c8 179 #define R92C_BAR_MODE_CTRL 0x4cc 180 #define R88E_TX_RPT_CTRL 0x4ec 181 /* EDCA Configuration. */ 182 #define R92C_EDCA_VO_PARAM 0x500 183 #define R92C_EDCA_VI_PARAM 0x504 184 #define R92C_EDCA_BE_PARAM 0x508 185 #define R92C_EDCA_BK_PARAM 0x50c 186 #define R92C_BCNTCFG 0x510 187 #define R92C_PIFS 0x512 188 #define R92C_RDG_PIFS 0x513 189 #define R92C_SIFS_CCK 0x514 190 #define R92C_SIFS_OFDM 0x516 191 #define R92C_AGGR_BREAK_TIME 0x51a 192 #define R92C_SLOT 0x51b 193 #define R92C_TX_PTCL_CTRL 0x520 194 #define R92C_TXPAUSE 0x522 195 #define R92C_DIS_TXREQ_CLR 0x523 196 #define R92C_RD_CTRL 0x524 197 #define R92C_TBTT_PROHIBIT 0x540 198 #define R92C_RD_NAV_NXT 0x544 199 #define R92C_NAV_PROT_LEN 0x546 200 #define R92C_BCN_CTRL 0x550 201 #define R92C_BCN_CTRL1 0x551 202 #define R92C_MBID_NUM 0x552 203 #define R92C_DUAL_TSF_RST 0x553 204 #define R92C_BCN_INTERVAL 0x554 205 #define R92C_DRVERLYINT 0x558 206 #define R92C_BCNDMATIM 0x559 207 #define R92C_ATIMWND 0x55a 208 #define R92C_USTIME_TSF 0x55c 209 #define R92C_BCN_MAX_ERR 0x55d 210 #define R92C_RXTSF_OFFSET_CCK 0x55e 211 #define R92C_RXTSF_OFFSET_OFDM 0x55f 212 #define R92C_TSFTR 0x560 213 #define R92C_INIT_TSFTR 0x564 214 #define R92C_PSTIMER 0x580 215 #define R92C_TIMER0 0x584 216 #define R92C_TIMER1 0x588 217 #define R92C_ACMHWCTRL 0x5c0 218 #define R92C_ACMRSTCTRL 0x5c1 219 #define R92C_ACMAVG 0x5c2 220 #define R92C_VO_ADMTIME 0x5c4 221 #define R92C_VI_ADMTIME 0x5c6 222 #define R92C_BE_ADMTIME 0x5c8 223 #define R92C_EDCA_RANDOM_GEN 0x5cc 224 #define R92C_SCH_TXCMD 0x5d0 225 /* WMAC Configuration. */ 226 #define R92C_APSD_CTRL 0x600 227 #define R92C_BWOPMODE 0x603 228 #define R92C_TCR 0x604 229 #define R92C_RCR 0x608 230 #define R92C_RX_PKT_LIMIT 0x60c 231 #define R92C_RX_DLK_TIME 0x60d 232 #define R92C_RX_DRVINFO_SZ 0x60f 233 #define R92C_MACID 0x610 234 #define R92C_BSSID 0x618 235 #define R92C_MAR 0x620 236 #define R92C_MBIDCAMCFG 0x628 237 #define R92C_USTIME_EDCA 0x638 238 #define R92C_MAC_SPEC_SIFS 0x63a 239 #define R92C_R2T_SIFS 0x63c 240 #define R92C_T2T_SIFS 0x63e 241 #define R92C_ACKTO 0x640 242 #define R92C_CTS2TO 0x641 243 #define R92C_EIFS 0x642 244 #define R92C_NAV_CTRL 0x650 245 #define R92C_BACAMCMD 0x654 246 #define R92C_BACAMCONTENT 0x658 247 #define R92C_LBDLY 0x660 248 #define R92C_FWDLY 0x661 249 #define R92C_RXERR_RPT 0x664 250 #define R92C_WMAC_TRXPTCL_CTL 0x668 251 #define R92C_CAMCMD 0x670 252 #define R92C_CAMWRITE 0x674 253 #define R92C_CAMREAD 0x678 254 #define R92C_CAMDBG 0x67c 255 #define R92C_SECCFG 0x680 256 #define R92C_WOW_CTRL 0x690 257 #define R92C_PSSTATUS 0x691 258 #define R92C_PS_RX_INFO 0x692 259 #define R92C_LPNAV_CTRL 0x694 260 #define R92C_WKFMCAM_CMD 0x698 261 #define R92C_WKFMCAM_RWD 0x69c 262 #define R92C_RXFLTMAP0 0x6a0 263 #define R92C_RXFLTMAP1 0x6a2 264 #define R92C_RXFLTMAP2 0x6a4 265 #define R92C_BCN_PSR_RPT 0x6a8 266 #define R92C_CALB32K_CTRL 0x6ac 267 #define R92C_PKT_MON_CTRL 0x6b4 268 #define R92C_BT_COEX_TABLE 0x6c0 269 #define R92C_WMAC_RESP_TXINFO 0x6d8 270 271 /* Bits for R92C_SYS_ISO_CTRL. */ 272 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 273 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 274 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 275 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 276 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 277 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 278 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 279 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 280 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 281 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 282 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 283 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 284 285 /* Bits for R92C_SYS_FUNC_EN. */ 286 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 287 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 288 #define R92C_SYS_FUNC_EN_USBA 0x0004 289 #define R92C_SYS_FUNC_EN_UPLL 0x0008 290 #define R92C_SYS_FUNC_EN_USBD 0x0010 291 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 292 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 293 #define R92C_SYS_FUNC_EN_PPLL 0x0080 294 #define R92C_SYS_FUNC_EN_PCIED 0x0100 295 #define R92C_SYS_FUNC_EN_DIOE 0x0200 296 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 297 #define R92C_SYS_FUNC_EN_DCORE 0x0800 298 #define R92C_SYS_FUNC_EN_ELDR 0x1000 299 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 300 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 301 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 302 303 /* Bits for R92C_APS_FSMCO. */ 304 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 305 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 306 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 307 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 308 #define R92C_APS_FSMCO_PDN_EN 0x00000010 309 #define R92C_APS_FSMCO_PDN_PL 0x00000020 310 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 311 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 312 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 313 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 314 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 315 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 316 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 317 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 318 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 319 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 320 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 321 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 322 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 323 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 324 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 325 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 326 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 327 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 328 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 329 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 330 331 /* Bits for R92C_SYS_CLKR. */ 332 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 333 #define R92C_SYS_CLKR_ANA8M 0x00000002 334 #define R92C_SYS_CLKR_MACSLP 0x00000010 335 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 336 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 337 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 338 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 339 #define R92C_SYS_CLKR_SEC_EN 0x00000400 340 #define R92C_SYS_CLKR_MAC_EN 0x00000800 341 #define R92C_SYS_CLKR_SYS_EN 0x00001000 342 #define R92C_SYS_CLKR_RING_EN 0x00002000 343 344 /* Bits for R92C_RSV_CTRL. */ 345 #define R92C_RSV_CTRL_WLOCK_ALL 0x01 346 #define R92C_RSV_CTRL_WLOCK_00 0x02 347 #define R92C_RSV_CTRL_WLOCK_04 0x04 348 #define R92C_RSV_CTRL_WLOCK_08 0x08 349 #define R92C_RSV_CTRL_WLOCK_40 0x10 350 #define R92C_RSV_CTRL_R_DIS_PRST_0 0x20 351 #define R92C_RSV_CTRL_R_DIS_PRST_1 0x40 352 #define R92C_RSV_CTRL_LOCK_ALL_EN 0x80 353 354 /* Bits for R92C_RF_CTRL. */ 355 #define R92C_RF_CTRL_EN 0x01 356 #define R92C_RF_CTRL_RSTB 0x02 357 #define R92C_RF_CTRL_SDMRSTB 0x04 358 359 /* Bits for R92C_LDOV12D_CTRL. */ 360 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 361 362 /* Bits for R92C_AFE_XTAL_CTRL. */ 363 #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 364 #define R92C_AFE_XTAL_CTRL_ADDR_S 11 365 366 /* Bits for R92C_EFUSE_CTRL. */ 367 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 368 #define R92C_EFUSE_CTRL_DATA_S 0 369 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 370 #define R92C_EFUSE_CTRL_ADDR_S 8 371 #define R92C_EFUSE_CTRL_VALID 0x80000000 372 373 /* Bits for R92C_GPIO_MUXCFG. */ 374 #define R92C_GPIO_MUXCFG_RFKILL 0x0008 375 #define R92C_GPIO_MUXCFG_ENBT 0x0020 376 377 /* Bits for R92C_GPIO_IO_SEL. */ 378 #define R92C_GPIO_IO_SEL_RFKILL 0x0008 379 380 /* Bits for R92C_LEDCFG0. */ 381 #define R92C_LEDCFG0_DIS 0x08 382 383 /* Bits for R92C_LEDCFG2. */ 384 #define R92C_LEDCFG2_EN 0x60 385 #define R92C_LEDCFG2_DIS 0x68 386 387 /* Bits for R92C_MCUFWDL. */ 388 #define R92C_MCUFWDL_EN 0x00000001 389 #define R92C_MCUFWDL_RDY 0x00000002 390 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 391 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 392 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 393 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 394 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 395 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ 396 #define R92C_MCUFWDL_PAGE_M 0x00070000 397 #define R92C_MCUFWDL_PAGE_S 16 398 #define R92C_MCUFWDL_CPRST 0x00800000 399 400 /* Bits for R88E_HIMR. */ 401 #define R88E_HIMR_CPWM 0x00000100 402 #define R88E_HIMR_CPWM2 0x00000200 403 #define R88E_HIMR_TBDER 0x04000000 404 #define R88E_HIMR_PSTIMEOUT 0x20000000 405 406 /* Bits for R88E_HIMRE.*/ 407 #define R88E_HIMRE_RXFOVW 0x00000100 408 #define R88E_HIMRE_TXFOVW 0x00000200 409 #define R88E_HIMRE_RXERR 0x00000400 410 #define R88E_HIMRE_TXERR 0x00000800 411 412 /* Bits for R92C_EFUSE_ACCESS. */ 413 #define R92C_EFUSE_ACCESS_OFF 0x00 414 #define R92C_EFUSE_ACCESS_ON 0x69 415 416 /* Bits for R92C_HPON_FSM. */ 417 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 418 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 419 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 420 421 /* Bits for R92C_SYS_CFG. */ 422 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 423 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 424 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 425 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 426 #define R92C_SYS_CFG_PCIRSTB 0x00000010 427 #define R92C_SYS_CFG_V15_VLD 0x00000020 428 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 429 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 430 #define R92C_SYS_CFG_BD_MAC2 0x00000200 431 #define R92C_SYS_CFG_BD_MAC1 0x00000400 432 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 433 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 434 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 435 #define R92C_SYS_CFG_BT_FUNC 0x00010000 436 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 437 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 438 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 439 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 440 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 441 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 442 #define R92C_SYS_CFG_TYPE_92C 0x08000000 443 444 /* Bits for R92C_CR. */ 445 #define R92C_CR_HCI_TXDMA_EN 0x00000001 446 #define R92C_CR_HCI_RXDMA_EN 0x00000002 447 #define R92C_CR_TXDMA_EN 0x00000004 448 #define R92C_CR_RXDMA_EN 0x00000008 449 #define R92C_CR_PROTOCOL_EN 0x00000010 450 #define R92C_CR_SCHEDULE_EN 0x00000020 451 #define R92C_CR_MACTXEN 0x00000040 452 #define R92C_CR_MACRXEN 0x00000080 453 #define R92C_CR_ENSEC 0x00000200 454 #define R92C_CR_CALTMR_EN 0x00000400 455 #define R92C_CR_NETTYPE_S 16 456 #define R92C_CR_NETTYPE_M 0x00030000 457 #define R92C_CR_NETTYPE_NOLINK 0 458 #define R92C_CR_NETTYPE_ADHOC 1 459 #define R92C_CR_NETTYPE_INFRA 2 460 #define R92C_CR_NETTYPE_AP 3 461 462 /* Bits for R92C_MSR. */ 463 #define R92C_MSR_NOLINK 0x00 464 #define R92C_MSR_ADHOC 0x01 465 #define R92C_MSR_INFRA 0x02 466 #define R92C_MSR_AP 0x03 467 #define R92C_MSR_MASK (~R92C_MSR_AP) 468 469 /* Bits for R92C_PBP. */ 470 #define R92C_PBP_PSRX_M 0x0f 471 #define R92C_PBP_PSRX_S 0 472 #define R92C_PBP_PSTX_M 0xf0 473 #define R92C_PBP_PSTX_S 4 474 #define R92C_PBP_64 0 475 #define R92C_PBP_128 1 476 #define R92C_PBP_256 2 477 #define R92C_PBP_512 3 478 #define R92C_PBP_1024 4 479 480 /* Bits for R92C_TRXDMA_CTRL. */ 481 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 482 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 483 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 484 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 485 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 486 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 487 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 488 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 489 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 490 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 491 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 492 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 493 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 494 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 495 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 496 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 497 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 498 #define R92C_TRXDMA_CTRL_QMAP_S 4 499 /* Shortcuts. */ 500 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 501 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 502 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 503 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 504 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 505 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 506 507 /* Bits for R92C_LLT_INIT. */ 508 #define R92C_LLT_INIT_DATA_M 0x000000ff 509 #define R92C_LLT_INIT_DATA_S 0 510 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 511 #define R92C_LLT_INIT_ADDR_S 8 512 #define R92C_LLT_INIT_OP_M 0xc0000000 513 #define R92C_LLT_INIT_OP_S 30 514 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 515 #define R92C_LLT_INIT_OP_WRITE 1 516 #define R92C_LLT_INIT_OP_READ 2 517 518 /* Bits for R92C_RQPN. */ 519 #define R92C_RQPN_HPQ_M 0x000000ff 520 #define R92C_RQPN_HPQ_S 0 521 #define R92C_RQPN_LPQ_M 0x0000ff00 522 #define R92C_RQPN_LPQ_S 8 523 #define R92C_RQPN_PUBQ_M 0x00ff0000 524 #define R92C_RQPN_PUBQ_S 16 525 #define R92C_RQPN_LD 0x80000000 526 527 /* Bits for R92C_TDECTRL. */ 528 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 529 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 530 531 /* Bits for R92C_FWHW_TXQ_CTRL. */ 532 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 533 534 /* Bits for R92C_SPEC_SIFS. */ 535 #define R92C_SPEC_SIFS_CCK_M 0x00ff 536 #define R92C_SPEC_SIFS_CCK_S 0 537 #define R92C_SPEC_SIFS_OFDM_M 0xff00 538 #define R92C_SPEC_SIFS_OFDM_S 8 539 540 /* Bits for R92C_RL. */ 541 #define R92C_RL_LRL_M 0x003f 542 #define R92C_RL_LRL_S 0 543 #define R92C_RL_SRL_M 0x3f00 544 #define R92C_RL_SRL_S 8 545 546 /* Bits for R92C_RRSR. */ 547 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 548 #define R92C_RRSR_RATE_BITMAP_S 0 549 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 550 #define R92C_RRSR_RATE_ALL 0xfffff 551 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 552 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 553 #define R92C_RRSR_SHORT 0x00800000 554 555 /* Bits for R88E_TX_RPT_CTRL. */ 556 #define R88E_TX_RPT_CTRL_EN 0x01 557 #define R88E_TX_RPT_CTRL_TIMER_EN 0x02 558 559 /* Bits for R92C_EDCA_XX_PARAM. */ 560 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 561 #define R92C_EDCA_PARAM_AIFS_S 0 562 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 563 #define R92C_EDCA_PARAM_ECWMIN_S 8 564 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 565 #define R92C_EDCA_PARAM_ECWMAX_S 12 566 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 567 #define R92C_EDCA_PARAM_TXOP_S 16 568 569 /* Bits for R92C_ACMHWCTRL */ 570 #define R92C_ACMHW_HWEN 0x01 571 #define R92C_ACMHW_BEQEN 0x02 572 #define R92C_ACMHW_VIQEN 0x04 573 #define R92C_ACMHW_VOQEN 0x08 574 #define R92C_ACMHW_BEQSTATUS 0x10 575 #define R92C_ACMHW_VIQSTATUS 0x20 576 #define R92C_ACMHW_VOQSTATUS 0x40 577 578 /* Bits for R92C_TXPAUSE. */ 579 #define R92C_TXPAUSE_AC_VO 0x01 580 #define R92C_TXPAUSE_AC_VI 0x02 581 #define R92C_TXPAUSE_AC_BE 0x04 582 #define R92C_TXPAUSE_AC_BK 0x08 583 #define R92C_TXPAUSE_MGNT 0x10 584 #define R92C_TXPAUSE_HIGH 0x20 585 #define R92C_TXPAUSE_BCN 0x40 586 #define R92C_TXPAUSE_BCN_HIGH_MGNT 0x80 587 588 #define R92C_TXPAUSE_ALL (R92C_TXPAUSE_AC_VO | R92C_TXPAUSE_AC_VI | \ 589 R92C_TXPAUSE_AC_BE | R92C_TXPAUSE_AC_BK | \ 590 R92C_TXPAUSE_MGNT | R92C_TXPAUSE_HIGH | \ 591 R92C_TXPAUSE_BCN | R92C_TXPAUSE_BCN_HIGH_MGNT) 592 593 /* Bits for R92C_BCN_CTRL. */ 594 #define R92C_BCN_CTRL_EN_MBSSID 0x02 595 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 596 #define R92C_BCN_CTRL_EN_BCN 0x08 597 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 598 599 /* Bits for R92C_DRVERLYINT. */ 600 #define R92C_DRVERLYINT_INIT_TIME 0x05 601 602 /* Bits for R92C_BCNDMATIM. */ 603 #define R92C_BCNDMATIM_INIT_TIME 0x02 604 605 /* Bits for R92C_APSD_CTRL. */ 606 #define R92C_APSD_CTRL_OFF 0x40 607 #define R92C_APSD_CTRL_OFF_STATUS 0x80 608 609 /* Bits for R92C_BWOPMODE. */ 610 #define R92C_BWOPMODE_11J 0x01 611 #define R92C_BWOPMODE_5G 0x02 612 #define R92C_BWOPMODE_20MHZ 0x04 613 614 /* Bits for R92C_TCR. */ 615 #define R92C_TCR_TSFRST 0x00000001 616 #define R92C_TCR_DIS_GCLK 0x00000002 617 #define R92C_TCR_PAD_SEL 0x00000004 618 #define R92C_TCR_PWR_ST 0x00000040 619 #define R92C_TCR_PWRBIT_OW_EN 0x00000080 620 #define R92C_TCR_ACRC 0x00000100 621 #define R92C_TCR_CFENDFORM 0x00000200 622 #define R92C_TCR_ICV 0x00000400 623 624 /* Bits for R92C_RCR. */ 625 #define R92C_RCR_AAP 0x00000001 // Accept all unicast packet 626 #define R92C_RCR_APM 0x00000002 // Accept physical match packet 627 #define R92C_RCR_AM 0x00000004 // Accept multicast packet 628 #define R92C_RCR_AB 0x00000008 // Accept broadcast packet 629 #define R92C_RCR_ADD3 0x00000010 // Accept address 3 match packet 630 #define R92C_RCR_APWRMGT 0x00000020 // Accept power management packet 631 #define R92C_RCR_CBSSID_DATA 0x00000040 // Accept BSSID match packet (Data) 632 #define R92C_RCR_CBSSID_BCN 0x00000080 // Accept BSSID match packet (Rx beacon, probe rsp) 633 #define R92C_RCR_ACRC32 0x00000100 // Accept CRC32 error packet 634 #define R92C_RCR_AICV 0x00000200 // Accept ICV error packet 635 #define R92C_RCR_ADF 0x00000800 // Accept data type frame 636 #define R92C_RCR_ACF 0x00001000 // Accept control type frame 637 #define R92C_RCR_AMF 0x00002000 // Accept management type frame 638 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 // MFC<--HTC=1 MFC-->HTC=0 639 #define R92C_RCR_MFBEN 0x00400000 640 #define R92C_RCR_LSIGEN 0x00800000 641 #define R92C_RCR_ENMBID 0x01000000 // Enable Multiple BssId 642 #define R92C_RCR_APP_BA_SSN 0x08000000 // Accept BA SSN 643 #define R92C_RCR_APP_PHYSTS 0x10000000 644 #define R92C_RCR_APP_ICV 0x20000000 645 #define R92C_RCR_APP_MIC 0x40000000 646 #define R92C_RCR_APPFCS 0x80000000 // WMAC append FCS after payload 647 648 /* Bits for R92C_WMAC_TRXPTCL_CTL. */ 649 #define R92C_WMAC_TRXPTCL_CTL_SHORT 0x00020000 650 651 /* Bits for R92C_CAMCMD. */ 652 #define R92C_CAMCMD_ADDR_M 0x0000ffff 653 #define R92C_CAMCMD_ADDR_S 0 654 #define R92C_CAMCMD_WRITE 0x00010000 655 #define R92C_CAMCMD_CLR 0x40000000 656 #define R92C_CAMCMD_POLLING 0x80000000 657 658 /* IMR */ 659 660 /*Beacon DMA interrupt 6 */ 661 #define R92C_IMR_BCNDMAINT6 0x80000000 662 /*Beacon DMA interrupt 5 */ 663 #define R92C_IMR_BCNDMAINT5 0x40000000 664 /*Beacon DMA interrupt 4 */ 665 #define R92C_IMR_BCNDMAINT4 0x20000000 666 /*Beacon DMA interrupt 3 */ 667 #define R92C_IMR_BCNDMAINT3 0x10000000 668 /*Beacon DMA interrupt 2 */ 669 #define R92C_IMR_BCNDMAINT2 0x08000000 670 /*Beacon DMA interrupt 1 */ 671 #define R92C_IMR_BCNDMAINT1 0x04000000 672 /*Beacon Queue DMA OK interrupt 8 */ 673 #define R92C_IMR_BCNDOK8 0x02000000 674 /*Beacon Queue DMA OK interrupt 7 */ 675 #define R92C_IMR_BCNDOK7 0x01000000 676 /*Beacon Queue DMA OK interrupt 6 */ 677 #define R92C_IMR_BCNDOK6 0x00800000 678 /*Beacon Queue DMA OK interrupt 5 */ 679 #define R92C_IMR_BCNDOK5 0x00400000 680 /*Beacon Queue DMA OK interrupt 4 */ 681 #define R92C_IMR_BCNDOK4 0x00200000 682 /*Beacon Queue DMA OK interrupt 3 */ 683 #define R92C_IMR_BCNDOK3 0x00100000 684 /*Beacon Queue DMA OK interrupt 2 */ 685 #define R92C_IMR_BCNDOK2 0x00080000 686 /*Beacon Queue DMA OK interrupt 1 */ 687 #define R92C_IMR_BCNDOK1 0x00040000 688 /*Timeout interrupt 2 */ 689 #define R92C_IMR_TIMEOUT2 0x00020000 690 /*Timeout interrupt 1 */ 691 #define R92C_IMR_TIMEOUT1 0x00010000 692 /*Transmit FIFO Overflow */ 693 #define R92C_IMR_TXFOVW 0x00008000 694 /*Power save time out interrupt */ 695 #define R92C_IMR_PSTIMEOUT 0x00004000 696 /*Beacon DMA interrupt 0 */ 697 #define R92C_IMR_BCNINT 0x00002000 698 /*Receive FIFO Overflow */ 699 #define R92C_IMR_RXFOVW 0x00001000 700 /*Receive Descriptor Unavailable */ 701 #define R92C_IMR_RDU 0x00000800 702 /*For 92C,ATIM Window End interrupt */ 703 #define R92C_IMR_ATIMEND 0x00000400 704 /*Beacon Queue DMA OK interrupt */ 705 #define R92C_IMR_BDOK 0x00000200 706 /*High Queue DMA OK interrupt */ 707 #define R92C_IMR_HIGHDOK 0x00000100 708 /*Transmit Beacon OK interrupt */ 709 #define R92C_IMR_TBDOK 0x00000080 710 /*Management Queue DMA OK interrupt */ 711 #define R92C_IMR_MGNTDOK 0x00000040 712 /*For 92C,Transmit Beacon Error interrupt */ 713 #define R92C_IMR_TBDER 0x00000020 714 /*AC_BK DMA OK interrupt */ 715 #define R92C_IMR_BKDOK 0x00000010 716 /*AC_BE DMA OK interrupt */ 717 #define R92C_IMR_BEDOK 0x00000008 718 /*AC_VI DMA OK interrupt */ 719 #define R92C_IMR_VIDOK 0x00000004 720 /*AC_VO DMA interrupt */ 721 #define R92C_IMR_VODOK 0x00000002 722 /*Receive DMA OK interrupt */ 723 #define R92C_IMR_ROK 0x00000001 724 725 #define R92C_IBSS_INT_MASK (R92C_IMR_BCNINT | R92C_IMR_TBDOK | \ 726 R92C_IMR_TBDER) 727 728 729 /* 730 * Baseband registers. 731 */ 732 #define R92C_FPGA0_RFMOD 0x800 733 #define R92C_FPGA0_TXINFO 0x804 734 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 735 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 736 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 737 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 738 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 739 #define R92C_FPGA0_XA_HSSIPARAM1 0x820 740 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 741 #define R92C_FPGA0_XCD_SWITCHCTL 0x85c 742 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 743 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 744 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 745 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 746 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 747 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 748 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 749 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 750 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 751 #define R92C_FPGA0_ANAPARAM2 0x884 752 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 753 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 754 #define R92C_FPGA1_RFMOD 0x900 755 #define R92C_FPGA1_TXINFO 0x90c 756 #define R92C_CCK0_SYSTEM 0xa00 757 #define R92C_CCK0_AFESETTING 0xa04 758 #define R92C_CONFIG_ANT_A 0xb68 759 #define R92C_CONFIG_ANT_B 0xb6c 760 #define R92C_OFDM0_TRXPATHENA 0xc04 761 #define R92C_OFDM0_TRMUXPAR 0xc08 762 #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) 763 #define R92C_OFDM0_ECCATHRESHOLD 0xc4c 764 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 765 #define R92C_OFDM0_AGCPARAM1 0xc70 766 #define R92C_OFDM0_AGCRSSITABLE 0xc78 767 #define R92C_OFDM0_HTSTFAGC 0xc7c 768 #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) 769 #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) 770 #define R92C_OFDM0_RXIQEXTANTA 0xca0 771 #define R92C_OFDM1_LSTF 0xd00 772 #define R92C_FPGA0_IQK 0xe28 773 #define R92C_TX_IQK 0xe40 774 #define R92C_RX_IQK 0xe44 775 #define R92C_BLUETOOTH 0xe6c 776 #define R92C_RX_WAIT_CCA 0xe70 777 #define R92C_TX_CCK_RFON 0xe74 778 #define R92C_TX_CCK_BBON 0xe78 779 #define R92C_TX_OFDM_RFON 0xe7c 780 #define R92C_TX_OFDM_BBON 0xe80 781 #define R92C_TX_TO_RX 0xe84 782 #define R92C_TX_TO_TX 0xe88 783 #define R92C_RX_CCK 0xe8c 784 #define R92C_RX_OFDM 0xed0 785 #define R92C_RX_WAIT_RIFS 0xed4 786 #define R92C_RX_TO_RX 0xed8 787 #define R92C_STANDBY 0xedc 788 #define R92C_SLEEP 0xee0 789 #define R92C_PMPD_ANAEN 0xeec 790 791 /* Bits for R92C_FPGA[01]_RFMOD. */ 792 #define R92C_RFMOD_40MHZ 0x00000001 793 #define R92C_RFMOD_JAPAN 0x00000002 794 #define R92C_RFMOD_CCK_TXSC 0x00000030 795 #define R92C_RFMOD_CCK_EN 0x01000000 796 #define R92C_RFMOD_OFDM_EN 0x02000000 797 798 /* Bits for R92C_HSSI_PARAM1(i). */ 799 #define R92C_HSSI_PARAM1_PI 0x00000100 800 801 /* Bits for R92C_HSSI_PARAM2(i). */ 802 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 803 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 804 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 805 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 806 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 807 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 808 809 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 810 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 811 #define R92C_TXAGC_A_CCK1_S 8 812 813 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 814 #define R92C_TXAGC_B_CCK11_M 0x000000ff 815 #define R92C_TXAGC_B_CCK11_S 0 816 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 817 #define R92C_TXAGC_A_CCK2_S 8 818 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 819 #define R92C_TXAGC_A_CCK55_S 16 820 #define R92C_TXAGC_A_CCK11_M 0xff000000 821 #define R92C_TXAGC_A_CCK11_S 24 822 823 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 824 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 825 #define R92C_TXAGC_B_CCK1_S 8 826 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 827 #define R92C_TXAGC_B_CCK2_S 16 828 #define R92C_TXAGC_B_CCK55_M 0xff000000 829 #define R92C_TXAGC_B_CCK55_S 24 830 831 /* Bits for R92C_TXAGC_RATE18_06(x). */ 832 #define R92C_TXAGC_RATE06_M 0x000000ff 833 #define R92C_TXAGC_RATE06_S 0 834 #define R92C_TXAGC_RATE09_M 0x0000ff00 835 #define R92C_TXAGC_RATE09_S 8 836 #define R92C_TXAGC_RATE12_M 0x00ff0000 837 #define R92C_TXAGC_RATE12_S 16 838 #define R92C_TXAGC_RATE18_M 0xff000000 839 #define R92C_TXAGC_RATE18_S 24 840 841 /* Bits for R92C_TXAGC_RATE54_24(x). */ 842 #define R92C_TXAGC_RATE24_M 0x000000ff 843 #define R92C_TXAGC_RATE24_S 0 844 #define R92C_TXAGC_RATE36_M 0x0000ff00 845 #define R92C_TXAGC_RATE36_S 8 846 #define R92C_TXAGC_RATE48_M 0x00ff0000 847 #define R92C_TXAGC_RATE48_S 16 848 #define R92C_TXAGC_RATE54_M 0xff000000 849 #define R92C_TXAGC_RATE54_S 24 850 851 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 852 #define R92C_TXAGC_MCS00_M 0x000000ff 853 #define R92C_TXAGC_MCS00_S 0 854 #define R92C_TXAGC_MCS01_M 0x0000ff00 855 #define R92C_TXAGC_MCS01_S 8 856 #define R92C_TXAGC_MCS02_M 0x00ff0000 857 #define R92C_TXAGC_MCS02_S 16 858 #define R92C_TXAGC_MCS03_M 0xff000000 859 #define R92C_TXAGC_MCS03_S 24 860 861 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 862 #define R92C_TXAGC_MCS04_M 0x000000ff 863 #define R92C_TXAGC_MCS04_S 0 864 #define R92C_TXAGC_MCS05_M 0x0000ff00 865 #define R92C_TXAGC_MCS05_S 8 866 #define R92C_TXAGC_MCS06_M 0x00ff0000 867 #define R92C_TXAGC_MCS06_S 16 868 #define R92C_TXAGC_MCS07_M 0xff000000 869 #define R92C_TXAGC_MCS07_S 24 870 871 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 872 #define R92C_TXAGC_MCS08_M 0x000000ff 873 #define R92C_TXAGC_MCS08_S 0 874 #define R92C_TXAGC_MCS09_M 0x0000ff00 875 #define R92C_TXAGC_MCS09_S 8 876 #define R92C_TXAGC_MCS10_M 0x00ff0000 877 #define R92C_TXAGC_MCS10_S 16 878 #define R92C_TXAGC_MCS11_M 0xff000000 879 #define R92C_TXAGC_MCS11_S 24 880 881 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 882 #define R92C_TXAGC_MCS12_M 0x000000ff 883 #define R92C_TXAGC_MCS12_S 0 884 #define R92C_TXAGC_MCS13_M 0x0000ff00 885 #define R92C_TXAGC_MCS13_S 8 886 #define R92C_TXAGC_MCS14_M 0x00ff0000 887 #define R92C_TXAGC_MCS14_S 16 888 #define R92C_TXAGC_MCS15_M 0xff000000 889 #define R92C_TXAGC_MCS15_S 24 890 891 /* Bits for R92C_LSSI_PARAM(i). */ 892 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 893 #define R92C_LSSI_PARAM_DATA_S 0 894 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 895 #define R92C_LSSI_PARAM_ADDR_S 20 896 #define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 897 #define R88E_LSSI_PARAM_ADDR_S 20 898 899 /* Bits for R92C_FPGA0_ANAPARAM2. */ 900 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 901 902 /* Bits for R92C_LSSI_READBACK(i). */ 903 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 904 #define R92C_LSSI_READBACK_DATA_S 0 905 906 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 907 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 908 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 909 910 911 /* 912 * USB registers. 913 */ 914 #define R92C_USB_INFO 0xfe17 915 #define R92C_USB_SPECIAL_OPTION 0xfe55 916 #define R92C_USB_SPECIAL_OPTION 0xfe55 917 #define R92C_USB_HCPWM 0xfe57 918 #define R92C_USB_HRPWM 0xfe58 919 #define R92C_USB_DMA_AGG_TO 0xfe5b 920 #define R92C_USB_AGG_TO 0xfe5c 921 #define R92C_USB_AGG_TH 0xfe5d 922 #define R92C_USB_VID 0xfe60 923 #define R92C_USB_PID 0xfe62 924 #define R92C_USB_OPTIONAL 0xfe64 925 #define R92C_USB_EP 0xfe65 926 #define R92C_USB_PHY 0xfe68 /* XXX: linux-3.7.4(rtlwifi/rtl8192ce/reg.h) has 0xfe66 */ 927 #define R92C_USB_MAC_ADDR 0xfe70 928 #define R92C_USB_STRING 0xfe80 929 930 /* Bits for R92C_USB_SPECIAL_OPTION. */ 931 #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 932 #define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 933 934 /* Bits for R92C_USB_EP. */ 935 #define R92C_USB_EP_HQ_M 0x000f 936 #define R92C_USB_EP_HQ_S 0 937 #define R92C_USB_EP_NQ_M 0x00f0 938 #define R92C_USB_EP_NQ_S 4 939 #define R92C_USB_EP_LQ_M 0x0f00 940 #define R92C_USB_EP_LQ_S 8 941 942 /* Bits for R92C_RD_CTRL. */ 943 #define R92C_RD_CTRL_DIS_EDCA_CNT_DWN __BIT(11) 944 945 /* Bits for R92C_INIDATA_RATE_SEL. */ 946 #define R92C_RATE_SHORTGI __BIT(6) 947 948 949 /* 950 * Firmware base address. 951 */ 952 #define R92C_FW_START_ADDR 0x1000 953 #define R92C_FW_PAGE_SIZE 4096 954 955 956 /* 957 * RF (6052) registers. 958 */ 959 #define R92C_RF_AC 0x00 960 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 961 #define R92C_RF_POW_TRSW 0x05 962 #define R92C_RF_GAIN_RX 0x06 963 #define R92C_RF_GAIN_TX 0x07 964 #define R92C_RF_TXM_IDAC 0x08 965 #define R92C_RF_BS_IQGEN 0x0f 966 #define R92C_RF_MODE1 0x10 967 #define R92C_RF_MODE2 0x11 968 #define R92C_RF_RX_AGC_HP 0x12 969 #define R92C_RF_TX_AGC 0x13 970 #define R92C_RF_BIAS 0x14 971 #define R92C_RF_IPA 0x15 972 #define R92C_RF_POW_ABILITY 0x17 973 #define R92C_RF_CHNLBW 0x18 974 #define R92C_RF_RX_G1 0x1a 975 #define R92C_RF_RX_G2 0x1b 976 #define R92C_RF_RX_BB2 0x1c 977 #define R92C_RF_RX_BB1 0x1d 978 #define R92C_RF_RCK1 0x1e 979 #define R92C_RF_RCK2 0x1f 980 #define R92C_RF_TX_G(i) (0x20 + (i)) 981 #define R92C_RF_TX_BB1 0x23 982 #define R92C_RF_T_METER 0x24 983 #define R92C_RF_SYN_G(i) (0x25 + (i)) 984 #define R92C_RF_RCK_OS 0x30 985 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 986 987 /* Bits for R92C_RF_AC. */ 988 #define R92C_RF_AC_MODE_M 0x70000 989 #define R92C_RF_AC_MODE_S 16 990 #define R92C_RF_AC_MODE_STANDBY 1 991 992 /* Bits for R92C_RF_CHNLBW. */ 993 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 994 #define R92C_RF_CHNLBW_CHNL_S 0 995 #define R92C_RF_CHNLBW_BW20 0x00400 996 #define R88E_RF_CHNLBW_BW20 0x00c00 997 #define R92C_RF_CHNLBW_LCSTART 0x08000 998 999 1000 /* 1001 * CAM entries. 1002 */ 1003 #define R92C_CAM_ENTRY_COUNT 32 1004 1005 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 1006 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 1007 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 1008 1009 /* Bits for R92C_CAM_CTL0(i). */ 1010 #define R92C_CAM_KEYID_M 0x00000003 1011 #define R92C_CAM_KEYID_S 0 1012 #define R92C_CAM_ALGO_M 0x0000001c 1013 #define R92C_CAM_ALGO_S 2 1014 #define R92C_CAM_ALGO_NONE 0 1015 #define R92C_CAM_ALGO_WEP40 1 1016 #define R92C_CAM_ALGO_TKIP 2 1017 #define R92C_CAM_ALGO_AES 4 1018 #define R92C_CAM_ALGO_WEP104 5 1019 #define R92C_CAM_VALID 0x00008000 1020 #define R92C_CAM_MACLO_M 0xffff0000 1021 #define R92C_CAM_MACLO_S 16 1022 1023 /* Rate adaptation modes. */ 1024 #define R92C_RAID_11BGN 0 1025 #define R92C_RAID_11GN 1 1026 #define R92C_RAID_11N 3 1027 #define R92C_RAID_11BG 4 1028 #define R92C_RAID_11G 5 /* "pure" 11g */ 1029 #define R92C_RAID_11B 6 1030 1031 1032 /* Macros to access unaligned little-endian memory. */ 1033 #define LE_READ_2(x) ((x)[0] | ((x)[1] << 8)) 1034 #define LE_READ_4(x) ((x)[0] | ((x)[1] << 8) | ((x)[2] << 16) | \ 1035 ((uint32_t)((x)[3]) << 24)) 1036 1037 /* 1038 * Macros to access subfields in registers. 1039 */ 1040 /* Mask and Shift (getter). */ 1041 #define MS(val, field) \ 1042 (((val) & field##_M) >> field##_S) 1043 1044 /* Shift and Mask (setter). */ 1045 #define SM(field, val) \ 1046 (((val) << field##_S) & field##_M) 1047 1048 /* Rewrite. */ 1049 #define RW(var, field, val) \ 1050 (((var) & ~field##_M) | SM(field, val)) 1051 1052 /* 1053 * Firmware image header. 1054 */ 1055 struct r92c_fw_hdr { 1056 /* QWORD0 */ 1057 uint16_t signature; 1058 uint8_t category; 1059 uint8_t function; 1060 uint16_t version; 1061 uint16_t subversion; 1062 /* QWORD1 */ 1063 uint8_t month; 1064 uint8_t date; 1065 uint8_t hour; 1066 uint8_t minute; 1067 uint16_t ramcodesize; 1068 uint16_t reserved2; 1069 /* QWORD2 */ 1070 uint32_t svnidx; 1071 uint32_t reserved3; 1072 /* QWORD3 */ 1073 uint32_t reserved4; 1074 uint32_t reserved5; 1075 } __packed; 1076 1077 /* 1078 * Host to firmware commands. 1079 */ 1080 struct r92c_fw_cmd { 1081 uint8_t id; 1082 #define R92C_CMD_AP_OFFLOAD 0 1083 #define R92C_CMD_SET_PWRMODE 1 1084 #define R92C_CMD_JOINBSS_RPT 2 1085 #define R92C_CMD_RSVD_PAGE 3 1086 #define R92C_CMD_RSSI 4 1087 #define R92C_CMD_RSSI_SETTING 5 1088 #define R92C_CMD_MACID_CONFIG 6 1089 #define R92C_CMD_MACID_PS_MODE 7 1090 #define R92C_CMD_P2P_PS_OFFLOAD 8 1091 #define R92C_CMD_SELECTIVE_SUSPEND 9 1092 #define R92C_CMD_USB_SUSPEND 43 1093 #define R92C_CMD_FLAG_EXT 0x80 1094 1095 uint8_t msg[5]; 1096 } __packed; 1097 1098 /* Structure for R92C_CMD_RSSI_SETTING. */ 1099 struct r92c_fw_cmd_rssi { 1100 uint8_t macid; 1101 uint8_t reserved; 1102 uint8_t pwdb; 1103 } __packed; 1104 1105 /* Structure for R92C_CMD_MACID_CONFIG. */ 1106 struct r92c_fw_cmd_macid_cfg { 1107 uint32_t mask; 1108 uint8_t macid; 1109 #define RTWN_MACID_BSS 0 1110 #define RTWN_MACID_BC 4 /* Broadcast. */ 1111 #define RTWN_MACID_VALID 0x80 1112 #define RTWN_MACID_SHORTGI 0x20 1113 } __packed; 1114 1115 /* Structure for R92C_CMD_SET_PWRMODE. */ 1116 struct r92c_fw_cmd_setpwrmode { 1117 uint8_t mode; 1118 uint8_t smartps; 1119 uint8_t bcn_time; /* 100ms increments */ 1120 } __packed; 1121 1122 #define R92E_CMD_KEEP_ALIVE 0x03 1123 #define R92E_CMD_SET_PWRMODE 0x20 1124 #define R92E_CMD_RSSI_REPORT 0x42 1125 1126 /* Structure for R92E_CMD_KEEP_ALIVE. */ 1127 struct r92e_fw_cmd_keepalive { 1128 uint8_t mode; 1129 uint8_t period; 1130 } __packed; 1131 1132 /* Structure for R92E_CMD_SET_PWRMODE. */ 1133 struct r92e_fw_cmd_setpwrmode { 1134 uint8_t mode; 1135 #define FWMODE_ACTIVE 0 1136 #define FWMODE_LOW_POWER 1 1137 #define FWMODE_WMMPS 2 1138 uint8_t smartps; 1139 #define SRTPS_LOW_POWER 0 1140 #define SRTPS_POLL 0x10 1141 #define SRTPS_WMMPS 0x20 1142 uint8_t awake_int; /* 100ms increments. */ 1143 uint8_t all_queue_apsd; 1144 uint8_t pwr_state; 1145 #define PS_RFOFF 0x0 1146 #define PS_RFON 0x4 1147 #define PS_ALLON 0xc 1148 } __packed; 1149 1150 /* Structure for R92E_CMD_RSSI_REPORT. */ 1151 struct r92e_fw_cmd_rssi { 1152 uint8_t macid; 1153 uint8_t reserved; 1154 uint8_t pwdb; 1155 uint8_t reserved2; 1156 } __packed; 1157 1158 1159 /* 1160 * RTL8192CU ROM image. 1161 */ 1162 struct r92c_rom { 1163 uint16_t id; /* 0x8192 */ 1164 uint8_t reserved1[5]; 1165 uint8_t dbg_sel; 1166 uint16_t reserved2; 1167 uint16_t vid; 1168 uint16_t pid; 1169 uint8_t usb_opt; 1170 uint8_t ep_setting; 1171 uint16_t reserved3; 1172 uint8_t usb_phy; 1173 uint8_t reserved4[3]; 1174 uint8_t macaddr[6]; 1175 uint8_t string[61]; /* "Realtek" */ 1176 uint8_t subcustomer_id; 1177 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 1178 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 1179 uint8_t ht40_2s_tx_pwr_diff[3]; 1180 uint8_t ht20_tx_pwr_diff[3]; 1181 uint8_t ofdm_tx_pwr_diff[3]; 1182 uint8_t ht40_max_pwr[3]; 1183 uint8_t ht20_max_pwr[3]; 1184 uint8_t xtal_calib; 1185 uint8_t tssi[R92C_MAX_CHAINS]; 1186 uint8_t thermal_meter; 1187 uint8_t rf_opt1; 1188 #define R92C_ROM_RF1_REGULATORY_M 0x07 1189 #define R92C_ROM_RF1_REGULATORY_S 0 1190 #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1191 #define R92C_ROM_RF1_BOARD_TYPE_S 5 1192 #define R92C_BOARD_TYPE_DONGLE 0 1193 #define R92C_BOARD_TYPE_HIGHPA 1 1194 #define R92C_BOARD_TYPE_MINICARD 2 1195 #define R92C_BOARD_TYPE_SOLO 3 1196 #define R92C_BOARD_TYPE_COMBO 4 1197 1198 uint8_t rf_opt2; 1199 uint8_t rf_opt3; 1200 uint8_t rf_opt4; 1201 uint8_t channel_plan; 1202 uint8_t version; 1203 uint8_t curstomer_id; 1204 } __packed; 1205 1206 struct r88e_tx_pwr { 1207 uint8_t cck_tx_pwr[6]; 1208 uint8_t ht40_tx_pwr[5]; 1209 uint8_t ht20_ofdm_tx_pwr_diff; 1210 #define R88E_ROM_TXPWR_HT20_DIFF_M 0xf0 1211 #define R88E_ROM_TXPWR_HT20_DIFF_S 4 1212 #define R88E_ROM_TXPWR_OFDM_DIFF_M 0x0f 1213 #define R88E_ROM_TXPWR_OFDM_DIFF_S 0 1214 } __packed; 1215 1216 /* 1217 * RTL8188EU ROM image. 1218 */ 1219 struct r88e_rom { 1220 uint8_t reserved1[16]; 1221 struct r88e_tx_pwr txpwr; 1222 uint8_t reserved2[156]; 1223 uint8_t channel_plan; 1224 uint8_t xtal; 1225 uint8_t thermal_meter; 1226 uint8_t reserved3[6]; 1227 uint8_t rf_board_opt; 1228 uint8_t rf_feature_opt; 1229 uint8_t rf_bt_opt; 1230 uint8_t version; 1231 uint8_t customer_id; 1232 uint8_t reserved4[3]; 1233 uint8_t rf_ant_opt; 1234 uint8_t reserved5[6]; 1235 uint16_t vid; 1236 uint16_t pid; 1237 uint8_t usb_opt; 1238 uint8_t reserved6[2]; 1239 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1240 uint8_t reserved7[2]; 1241 uint8_t string[33]; /* "Realtek" */ 1242 uint8_t reserved8[256]; 1243 } __packed; 1244 1245 /* Rx PHY descriptor. */ 1246 struct r92c_rx_phystat { 1247 uint32_t phydw0; 1248 uint32_t phydw1; 1249 uint32_t phydw2; 1250 uint32_t phydw3; 1251 uint32_t phydw4; 1252 uint32_t phydw5; 1253 uint32_t phydw6; 1254 uint32_t phydw7; 1255 } __packed __aligned(4); 1256 1257 struct r88e_rx_phystat { 1258 uint8_t path_agc[2]; 1259 uint8_t ch_corr[2]; 1260 uint8_t sq_rpt; 1261 uint8_t agc_rpt; 1262 uint8_t rpt_b; 1263 uint8_t reserved1; 1264 uint8_t noise_power; 1265 int8_t path_cfotail[2]; 1266 uint8_t pcts_mask[2]; 1267 int8_t stream_rxevm[2]; 1268 uint8_t path_rxsnr[2]; 1269 uint8_t noise_power_db_lsb; 1270 uint8_t reserved2[3]; 1271 uint8_t stream_csi[2]; 1272 uint8_t stream_target_csi[2]; 1273 int8_t sig_evm; 1274 uint8_t reserved3; 1275 uint8_t reserved4; 1276 } __packed; 1277 1278 /* Rx PHY CCK descriptor. */ 1279 struct r92c_rx_cck { 1280 uint8_t adc_pwdb[4]; 1281 uint8_t sq_rpt; 1282 uint8_t agc_rpt; 1283 } __packed; 1284 1285 struct r88e_rx_cck { 1286 uint8_t path_agc[2]; 1287 uint8_t sig_qual; 1288 uint8_t agc_rpt; 1289 uint8_t rpt_b; 1290 uint8_t reserved1; 1291 uint8_t noise_power; 1292 uint8_t ath_cfotail[2]; 1293 uint8_t pcts_mask[2]; 1294 uint8_t stream_rxevm[2]; 1295 uint8_t path_rxsnr[2]; 1296 uint8_t noise_power_db_lsb; 1297 uint8_t reserved2[3]; 1298 uint8_t stream_csi[2]; 1299 uint8_t stream_target_csi[2]; 1300 uint8_t sig_evm; 1301 uint8_t reserved3; 1302 uint8_t reserved4; 1303 } __packed; 1304 1305 /* Rx MAC descriptor. */ 1306 struct r92c_rx_desc_pci { 1307 uint32_t rxdw0; 1308 uint32_t rxdw1; 1309 uint32_t rxdw2; 1310 uint32_t rxdw3; 1311 uint32_t rxdw4; 1312 uint32_t rxdw5; 1313 uint32_t rxbufaddr; 1314 uint32_t rxbufaddr64; 1315 } __packed __aligned(4); 1316 1317 struct r92c_rx_desc_usb { 1318 uint32_t rxdw0; 1319 uint32_t rxdw1; 1320 uint32_t rxdw2; 1321 uint32_t rxdw3; 1322 uint32_t rxdw4; 1323 uint32_t rxdw5; 1324 } __packed __aligned(4); 1325 1326 #define R92C_RXDW0_PKTLEN_M 0x00003fff 1327 #define R92C_RXDW0_PKTLEN_S 0 1328 #define R92C_RXDW0_CRCERR 0x00004000 1329 #define R92C_RXDW0_ICVERR 0x00008000 1330 #define R92C_RXDW0_INFOSZ_M 0x000f0000 1331 #define R92C_RXDW0_INFOSZ_S 16 1332 #define R92C_RXDW0_QOS 0x00800000 1333 #define R92C_RXDW0_SHIFT_M 0x03000000 1334 #define R92C_RXDW0_SHIFT_S 24 1335 #define R92C_RXDW0_PHYST 0x04000000 1336 #define R92C_RXDW0_DECRYPTED 0x08000000 1337 #define R92C_RXDW0_LS 0x10000000 1338 #define R92C_RXDW0_FS 0x20000000 1339 #define R92C_RXDW0_EOR 0x40000000 1340 #define R92C_RXDW0_OWN 0x80000000 1341 1342 #define R92C_RXDW2_PKTCNT_M 0x00ff0000 1343 #define R92C_RXDW2_PKTCNT_S 16 1344 #define R92E_RXDW2_PKTCNT_M 0x3fc00000 1345 #define R92E_RXDW2_PKTCNT_S 22 1346 1347 #define R92C_RXDW3_RATE_M 0x0000003f 1348 #define R92C_RXDW3_RATE_S 0 1349 #define R92C_RXDW3_HT 0x00000040 1350 #define R92C_RXDW3_HTC 0x00000400 1351 #define R88E_RXDW3_RPT_M 0x0000c000 1352 #define R88E_RXDW3_RPT_S 14 1353 #define R88E_RXDW3_RPT_RX 0 1354 #define R88E_RXDW3_RPT_TX1 1 1355 #define R88E_RXDW3_RPT_TX2 2 1356 #define R88E_RXDW3_RPT_HIS 3 1357 1358 /* Tx MAC descriptor. */ 1359 struct r92c_tx_desc_pci { 1360 uint32_t txdw0; 1361 uint32_t txdw1; 1362 uint32_t txdw2; 1363 uint16_t txdw3; 1364 uint16_t txdseq; 1365 uint32_t txdw4; 1366 uint32_t txdw5; 1367 uint32_t txdw6; 1368 uint16_t txbufsize; 1369 uint16_t pad; 1370 uint32_t txbufaddr; 1371 uint32_t txbufaddr64; 1372 uint32_t nextdescaddr; 1373 uint32_t nextdescaddr64; 1374 uint32_t reserved[4]; 1375 } __packed __aligned(4); 1376 1377 struct r92c_tx_desc_usb { 1378 uint32_t txdw0; 1379 uint32_t txdw1; 1380 uint32_t txdw2; 1381 uint16_t txdw3; 1382 uint16_t txdseq; 1383 uint32_t txdw4; 1384 uint32_t txdw5; 1385 uint32_t txdw6; 1386 uint16_t txdsum; 1387 uint16_t pad; 1388 uint32_t txdw7; 1389 uint16_t txdseq2; 1390 #define R92E_HWSEQ_SHIFT 11 1391 #define R92E_HWSEQ_MASK 0x00000fffff 1392 uint16_t txdw8; 1393 } __packed __aligned(4); 1394 1395 #define R92C_TXDW0_PKTLEN_M 0x0000ffff 1396 #define R92C_TXDW0_PKTLEN_S 0 1397 #define R92C_TXDW0_OFFSET_M 0x00ff0000 1398 #define R92C_TXDW0_OFFSET_S 16 1399 #define R92C_TXDW0_BMCAST 0x01000000 1400 #define R92C_TXDW0_LSG 0x04000000 1401 #define R92C_TXDW0_FSG 0x08000000 1402 #define R92C_TXDW0_OWN 0x80000000 1403 1404 #define R92C_TXDW1_MACID_M 0x0000001f 1405 #define R92C_TXDW1_MACID_S 0 1406 #define R88E_TXDW1_MACID_M 0x0000003f 1407 #define R88E_TXDW1_MACID_S 0 1408 #define R92C_TXDW1_AGGEN 0x00000020 1409 #define R92C_TXDW1_AGGBK 0x00000040 1410 #define R92C_TXDW1_QSEL_M 0x00001f00 1411 #define R92C_TXDW1_QSEL_S 8 1412 #define R92C_TXDW1_QSEL_BE 0x00 1413 #define R92C_TXDW1_QSEL_BK 0x02 1414 #define R92C_TXDW1_QSEL_VI 0x05 1415 #define R92C_TXDW1_QSEL_VO 0x07 1416 #define R92C_TXDW1_QSEL_BEACON 0x10 1417 #define R92C_TXDW1_QSEL_HIGH 0x11 1418 #define R92C_TXDW1_QSEL_MGNT 0x12 1419 #define R92C_TXDW1_QSEL_CMD 0x13 1420 #define R92C_TXDW1_RAID_M 0x000f0000 1421 #define R92C_TXDW1_RAID_S 16 1422 #define R92C_TXDW1_CIPHER_M 0x00c00000 1423 #define R92C_TXDW1_CIPHER_S 22 1424 #define R92C_TXDW1_CIPHER_NONE 0 1425 #define R92C_TXDW1_CIPHER_RC4 1 1426 #define R92C_TXDW1_CIPHER_AES 3 1427 #define R92C_TXDW1_PKTOFF_M 0x7c000000 1428 #define R92C_TXDW1_PKTOFF_S 26 1429 1430 #define R88E_TXDW2_AGGBK 0x00010000 1431 #define R92C_TXDW2_CCX_RPT 0x00080000 1432 1433 #define R92E_TXDW3_AGGBK 0x00000100 1434 1435 #define R92C_HWSEQ_EN 0x00008000 1436 1437 #define R92C_TXDW4_RTSRATE_M 0x0000003f 1438 #define R92C_TXDW4_RTSRATE_S 0 1439 #define R92C_TXDW4_QOS 0x00000040 1440 #define R92C_TXDW4_HWSEQ 0x00000080 1441 #define R92C_TXDW4_DRVRATE 0x00000100 1442 #define R92C_TXDW4_CTS2SELF 0x00000800 1443 #define R92C_TXDW4_RTSEN 0x00001000 1444 #define R92C_TXDW4_HWRTSEN 0x00002000 1445 #define R92C_TXDW4_SCO_M 0x003f0000 1446 #define R92C_TXDW4_SCO_S 20 1447 #define R92C_TXDW4_SCO_SCA 1 1448 #define R92C_TXDW4_SCO_SCB 2 1449 #define R92C_TXDW4_40MHZ 0x02000000 1450 1451 #define R92C_TXDW5_DATARATE_M 0x0000003f 1452 #define R92C_TXDW5_DATARATE_S 0 1453 #define R92C_TXDW5_SGI 0x00000040 1454 #define R92C_TXDW5_DATARATE_FBLIMIT_M 0x00001f00 1455 #define R92C_TXDW5_DATARATE_FBLIMIT_S 8 1456 #define R92C_TXDW5_RTSRATE_FBLIMIT_M 0x0001e000 1457 #define R92C_TXDW5_RTSRATE_FBLIMIT_S 13 1458 #define R92C_TXDW5_RETRY_LIMIT_ENABLE 0x00020000 1459 #define R92C_TXDW5_DATA_RETRY_LIMIT_M 0x00fc0000 1460 #define R92C_TXDW5_DATA_RETRY_LIMIT_S 18 1461 #define R92C_TXDW5_AGGNUM_M 0xff000000 1462 #define R92C_TXDW5_AGGNUM_S 24 1463 1464 /* Tx report (type 1). */ 1465 struct r88e_tx_rpt_ccx { 1466 uint8_t rptb0; 1467 #define R88E_RPTB6_PKT_NUM_M 0x0e 1468 #define R88E_RPTB6_PKT_NUM_S 1 1469 #define R88E_RPTB0_INT_CCX 0x80 1470 1471 uint8_t rptb1; 1472 #define R88E_RPTB1_MACID_M 0x3f 1473 #define R88E_RPTB1_MACID_S 0 1474 #define R88E_RPTB1_PKT_OK 0x40 1475 #define R88E_RPTB1_BMC 0x80 1476 1477 uint8_t rptb2; 1478 #define R88E_RPTB2_RETRY_CNT_M 0x3f 1479 #define R88E_RPTB2_RETRY_CNT_S 0 1480 #define R88E_RPTB2_LIFE_EXPIRE 0x40 1481 #define R88E_RPTB2_RETRY_OVER 0x80 1482 1483 uint8_t queue_time_low; 1484 uint8_t queue_time_high; 1485 uint8_t final_rate; 1486 uint8_t rptb6; 1487 #define R88E_RPTB6_QSEL_M 0xf0 1488 #define R88E_RPTB6_QSEL_S 4 1489 1490 uint8_t rptb7; 1491 } __packed; 1492 1493 /* 1494 * C2H event structure. 1495 */ 1496 #define R92C_C2H_MSG_MAX_LEN 16 1497 1498 struct r92c_c2h_evt { 1499 uint8_t evtb0; 1500 #define R92C_C2H_EVTB0_ID_M 0x0f 1501 #define R92C_C2H_EVTB0_ID_S 0 1502 #define R92C_C2H_EVTB0_LEN_M 0xf0 1503 #define R92C_C2H_EVTB0_LEN_S 4 1504 1505 uint8_t seq; 1506 1507 /* Followed by payload (see below). */ 1508 } __packed; 1509 1510 /* Bits for R92C_C2HEVT_CLEAR. */ 1511 #define R92C_C2HEVT_HOST_CLOSE 0x00 1512 #define R92C_C2HEVT_FW_CLOSE 0xff 1513 1514 /* 1515 * C2H event types. 1516 */ 1517 #define R92C_C2HEVT_DEBUG 0 1518 #define R92C_C2HEVT_TX_REPORT 3 1519 #define R92C_C2HEVT_EXT_RA_RPT 6 1520 1521 /* Structure for R92C_C2H_EVT_TX_REPORT event. */ 1522 struct r92c_c2h_tx_rpt { 1523 uint8_t rptb0; 1524 #define R92C_RPTB0_RETRY_CNT_M 0x3f 1525 #define R92C_RPTB0_RETRY_CNT_S 0 1526 1527 uint8_t rptb1; /* XXX junk */ 1528 #define R92C_RPTB1_RTS_RETRY_CNT_M 0x3f 1529 #define R92C_RPTB1_RTS_RETRY_CNT_S 0 1530 1531 uint8_t queue_time_low; 1532 uint8_t queue_time_high; 1533 uint8_t rptb4; 1534 #define R92C_RPTB4_MISSED_PKT_NUM_M 0x1f 1535 #define R92C_RPTB4_MISSED_PKT_NUM_S 0 1536 1537 uint8_t rptb5; 1538 #define R92C_RPTB5_MACID_M 0x1f 1539 #define R92C_RPTB5_MACID_S 0 1540 #define R92C_RPTB5_DES1_FRAGSSN_M 0xe0 1541 #define R92C_RPTB5_DES1_FRAGSSN_S 5 1542 1543 uint8_t rptb6; 1544 #define R92C_RPTB6_RPT_PKT_NUM_M 0x1f 1545 #define R92C_RPTB6_RPT_PKT_NUM_S 0 1546 #define R92C_RPTB6_PKT_DROP 0x20 1547 #define R92C_RPTB6_LIFE_EXPIRE 0x40 1548 #define R92C_RPTB6_RETRY_OVER 0x80 1549 1550 uint8_t rptb7; 1551 #define R92C_RPTB7_EDCA_M 0x0f 1552 #define R92C_RPTB7_EDCA_S 0 1553 #define R92C_RPTB7_BMC 0x20 1554 #define R92C_RPTB7_PKT_OK 0x40 1555 #define R92C_RPTB7_INT_CCX 0x80 1556 } __packed; 1557 1558 #endif /* _DEV_IC_RTWNREG_H_ */ 1559