Searched refs:regl (Results 1 – 3 of 3) sorted by relevance
3604 pcireg_t regl, regh; in pci_conf_print_multicast_cap() local3629 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; in pci_conf_print_multicast_cap()3631 printf(" Base Address Register 0: 0x%08x\n", regl); in pci_conf_print_multicast_cap()3634 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); in pci_conf_print_multicast_cap()3635 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); in pci_conf_print_multicast_cap()3638 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; in pci_conf_print_multicast_cap()3640 printf(" Receive Register 0: 0x%08x\n", regl); in pci_conf_print_multicast_cap()3643 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; in pci_conf_print_multicast_cap()3645 printf(" Block All Register 0: 0x%08x\n", regl); in pci_conf_print_multicast_cap()3648 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; in pci_conf_print_multicast_cap()[all …]
4335 rtx regl = gen_rtx_REG (SFmode, i); in pa_expand_prologue() local4337 rtx setl = gen_rtx_SET (meml, regl); in pa_expand_prologue()
6567 int regl; in parse_sys_vldr_vstr() member6590 val = sysregs[i].regl | (sysregs[i].regh << 3); in parse_sys_vldr_vstr()