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Searched refs:op5 (Results 1 – 18 of 18) sorted by relevance

/netbsd/src/external/historical/nawk/dist/
Dawkgram.y385 { $$ = op5(GENSUB, NIL, (Node*)makedfa($3, 1), $5, $7, rectonode()); }
388 … $$ = op5(GENSUB, NIL, (Node *)makedfa(strnode($3), 1), $5, $7, rectonode());
391 $$ = op5(GENSUB, (Node *)1, $3, $5, $7, rectonode());
394 { $$ = op5(GENSUB, NIL, (Node*)makedfa($3, 1), $5, $7, $9); }
397 $$ = op5(GENSUB, NIL, (Node *)makedfa(strnode($3),1), $5,$7,$9);
400 $$ = op5(GENSUB, (Node *)1, $3, $5, $7, $9);
Dproto.h80 extern Node *op5(int, Node *, Node *, Node *, Node *, Node *);
Dparse.c186 Node *op5(int a, Node *b, Node *c, Node *d, Node *e, Node *f) in op5() function
DChangeLog68 * parse.c (node5, op5): New functions.
69 * proto.h (node5, op5): New declarations.
/netbsd/src/external/gpl3/binutils/dist/include/opcode/
Dnds32.h97 #define N16_TYPE55(op5, rt5, ra5) \ argument
98 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
121 #define N16_TYPE10(op5, imm10) \ argument
122 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
/netbsd/src/external/gpl3/gdb/dist/include/opcode/
Dnds32.h97 #define N16_TYPE55(op5, rt5, ra5) \ argument
98 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
121 #define N16_TYPE10(op5, imm10) \ argument
122 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
/netbsd/src/external/gpl3/gcc/dist/gcc/config/rs6000/
Dvsx.md1696 rtx op5 = gen_reg_rtx (DImode);
1700 emit_insn (gen_muldi3 (op5, op3, op4));
1704 emit_move_insn (op5, ret);
1715 emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
1745 rtx op5 = gen_reg_rtx (DImode);
1749 emit_insn (gen_divdi3 (op5, op3, op4));
1754 op5, LCT_NORMAL, DImode,
1757 emit_move_insn (op5, target);
1772 emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
1797 rtx op5 = gen_reg_rtx (DImode);
[all …]
/netbsd/src/external/gpl3/binutils/dist/cpu/
Dfr30.cpu147 (dnf f-op5 "5th bit of opcode" () 4 1)
262 ; insn-op5: bit 4 (5th bit origin 0)
264 (define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5
Dxstormy16.cpu261 (dnf f-op5 "opcode" () 16 4)
262 (define-normal-insn-enum insn-op5 "insn op enums" () OP5_ f-op5
264 (dnop bcond5 "branch condition opcode" () h-branchcond f-op5)
/netbsd/src/external/gpl3/gdb/dist/cpu/
Dfr30.cpu147 (dnf f-op5 "5th bit of opcode" () 4 1)
262 ; insn-op5: bit 4 (5th bit origin 0)
264 (define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5
Dxstormy16.cpu261 (dnf f-op5 "opcode" () 16 4)
262 (define-normal-insn-enum insn-op5 "insn op enums" () OP5_ f-op5
264 (dnop bcond5 "branch condition opcode" () h-branchcond f-op5)
/netbsd/src/external/gpl3/gcc/dist/gcc/
Dsimplify-rtx.cc8205 rtx op5 = make_test_reg (mode); in test_vec_merge() local
8210 rtx vm3 = gen_rtx_VEC_MERGE (mode, op4, op5, mask1); in test_vec_merge()
8244 ASSERT_RTX_EQ (gen_rtx_FMA (mode, op1, op3, op5), in test_vec_merge()
/netbsd/src/external/gpl3/gcc/dist/gcc/config/i386/
Di386-expand.cc15715 rtx ops[64], op0, op1, op2, op3, op4, op5; in ix86_expand_vector_init_general() local
15815 op5 = gen_reg_rtx (half_mode); in ix86_expand_vector_init_general()
15825 emit_insn (gen_rtx_SET (op5, gen_rtx_VEC_CONCAT (half_mode, op2, op3))); in ix86_expand_vector_init_general()
15826 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_CONCAT (mode, op4, op5))); in ix86_expand_vector_init_general()
/netbsd/src/external/gpl3/gcc/dist/gcc/config/arm/
Darm.md12429 rtx op5 = gen_reg_rtx (SImode);
12432 op2, op3, op4, op5));
/netbsd/src/external/gpl3/gcc/dist/gcc/config/s390/
Ds390.md8835 [; Make a backup of op5 first
8837 ; Setting op2 here might clobber op5
/netbsd/src/external/gpl3/gcc/dist/gcc/doc/
Dmd.texi7084 op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i];
Dgccint.info28228 op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i];
/netbsd/src/external/gpl3/gcc/dist/
DMD5SUMS12029 c0f35a8e0a449b69b0039186b48a3942 gcc/testsuite/g++.dg/conversion/op5.C