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Searched refs:i915_reg_t (Results 1 – 16 of 16) sorted by relevance

/netbsd/src/sys/external/bsd/drm2/dist/drm/i915/
Dintel_uncore.h83 i915_reg_t r);
85 i915_reg_t r);
88 i915_reg_t r, bool trace);
90 i915_reg_t r, bool trace);
92 i915_reg_t r, bool trace);
94 i915_reg_t r, bool trace);
97 i915_reg_t r, u8 val, bool trace);
99 i915_reg_t r, u16 val, bool trace);
101 i915_reg_t r, u32 val, bool trace);
227 i915_reg_t reg, unsigned int op);
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Di915_irq.h126 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
127 i915_reg_t iir, i915_reg_t ier);
132 i915_reg_t imr, u32 imr_val,
133 i915_reg_t ier, u32 ier_val,
134 i915_reg_t iir);
Dintel_uncore.c946 static const i915_reg_t gen8_shadowed_regs[] = {
956 static const i915_reg_t gen11_shadowed_regs[] = {
970 static const i915_reg_t gen12_shadowed_regs[] = {
984 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) in mmio_reg_cmp()
999 const i915_reg_t *regs = gen##x##_shadowed_regs; \
1009 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) in gen6_reg_write_fw_domains()
1193 const i915_reg_t reg, in __unclaimed_reg_debug()
1207 const i915_reg_t reg, in unclaimed_reg_debug()
1236 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1244 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
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Di915_gem_fence_reg.c81 i915_reg_t fence_reg_lo, fence_reg_hi; in i965_write_fence_reg()
168 i915_reg_t reg = FENCE_REG(fence->id); in i915_write_fence_reg()
200 i915_reg_t reg = FENCE_REG(fence->id); in i830_write_fence_reg()
Di915_irq.c177 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, in gen3_irq_reset()
178 i915_reg_t iir, i915_reg_t ier) in gen3_irq_reset()
209 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) in gen3_assert_iir_is_zero()
240 i915_reg_t imr, u32 imr_val, in gen3_irq_init()
241 i915_reg_t ier, u32 ier_val, in gen3_irq_init()
242 i915_reg_t iir) in gen3_irq_init()
462 i915_reg_t reg = PIPESTAT(pipe); in i915_enable_pipestat()
485 i915_reg_t reg = PIPESTAT(pipe); in i915_disable_pipestat()
591 i915_reg_t high_frame, low_frame; in i915_get_vblank_counter()
936 i915_reg_t reg; in ivb_parity_work()
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Di915_perf_types.h38 i915_reg_t addr;
Di915_perf.c905 i915_reg_t oaheadptr; in gen8_append_oa_reports()
961 i915_reg_t oastatus_reg; in gen8_oa_read()
1735 bool save, i915_reg_t reg, u32 offset, in save_restore_register()
2150 i915_reg_t reg) in oa_config_flex_reg()
2184 i915_reg_t flex_regs[] = { in gen8_update_reg_state_unlocked()
2210 i915_reg_t reg;
4033 static const i915_reg_t flex_eu_regs[] = { in gen8_is_valid_flex_addr()
Di915_sysfs.c54 i915_reg_t reg) in calc_residency()
Di915_drv.h346 i915_reg_t mmioaddr[20];
535 i915_reg_t gpio_reg;
Di915_cmd_parser.c573 i915_reg_t addr;
Di915_reg.h186 } i915_reg_t; typedef
188 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
192 static inline u32 i915_mmio_reg_offset(i915_reg_t reg) in i915_mmio_reg_offset()
197 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) in i915_mmio_reg_equal()
202 static inline bool i915_mmio_reg_valid(i915_reg_t reg) in i915_mmio_reg_valid()
Di915_gpu_error.c1161 i915_reg_t mmio; in engine_record_registers()
Di915_drv.c2416 i915_reg_t reg = VLV_GTLC_PW_STATUS; in vlv_wait_for_pw_status()
Di915_debugfs.c1090 const i915_reg_t reg) in print_rc6_res()
2284 i915_reg_t dc5_reg, dc6_reg = {}; in i915_dmc_info()
Dintel_pm.c5067 i915_reg_t reg, in skl_ddb_entry_write()
5077 i915_reg_t reg, in skl_write_wm_level()
5759 static const i915_reg_t wm0_pipe_reg[] = { in ilk_pipe_wm_get_hw_state()
/netbsd/src/sys/external/bsd/drm2/include/
Di915_trace.h262 trace_i915_reg_rw(bool write, i915_reg_t reg, uint64_t value, size_t len, in trace_i915_reg_rw()