Searched refs:gart_size (Results 1 – 5 of 5) sorted by relevance
632 dev_priv->gart_size) & 0xffff0000) | in radeon_cp_init_ring_buffer()780 dev_priv->gart_size); in radeon_set_igpgart()810 dev_priv->gart_size = 32*1024*1024; in radeon_set_igpgart()811 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & in radeon_set_igpgart()853 dev_priv->gart_size); in rs600_set_igpgart()880 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); in rs600_set_igpgart()887 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); in rs600_set_igpgart()927 dev_priv->gart_size); in radeon_set_pciegart()936 dev_priv->gart_size - 1); in radeon_set_pciegart()984 + dev_priv->gart_size - 1); in radeon_set_pcigart()[all …]
214 …600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); in r600_vm_flush_gart_range()233 …E(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); in r600_vm_init()284 …E(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); in r600_vm_init()375 …E(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); in r700_vm_init()414 …E(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); in r700_vm_init()1762 dev_priv->gart_size) & 0xffff0000) | in r600_cp_init_ring_buffer()2025 dev_priv->gart_size = init->gart_size; in r600_do_init_cp()2042 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && in r600_do_init_cp()2054 ((base + dev_priv->gart_size) & 0xfffffffful) < base) in r600_do_init_cp()2056 - dev_priv->gart_size; in r600_do_init_cp()[all …]
539 int gart_size; member
296 int gart_size; member436 u64 gart_end = gart_start + dev_priv->gart_size - 1; in radeon_check_offset()
73 if (off < (dev_priv->fb_size + dev_priv->gart_size)) { in radeon_check_and_fixup_offset()