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Searched refs:dev_priv (Results 1 – 25 of 128) sorted by relevance

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/netbsd/src/sys/external/bsd/drm2/dist/drm/vmwgfx/
Dvmwgfx_drv.c363 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) in vmw_dummy_query_bo_create() argument
380 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, in vmw_dummy_query_bo_create()
405 dev_priv->dummy_query_bo = vbo; in vmw_dummy_query_bo_create()
420 static int vmw_request_device_late(struct vmw_private *dev_priv) in vmw_request_device_late() argument
424 if (dev_priv->has_mob) { in vmw_request_device_late()
425 ret = vmw_otables_setup(dev_priv); in vmw_request_device_late()
433 if (dev_priv->cman) { in vmw_request_device_late()
434 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, in vmw_request_device_late()
437 struct vmw_cmdbuf_man *man = dev_priv->cman; in vmw_request_device_late()
439 dev_priv->cman = NULL; in vmw_request_device_late()
[all …]
Dvmwgfx_irq.c60 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_thread_fn() local
64 atomic_store_relaxed(&dev_priv->irqthread_scheduled, false); in vmw_thread_fn()
68 dev_priv->irqthread_pending)) { in vmw_thread_fn()
69 spin_lock(&dev_priv->fence_lock); in vmw_thread_fn()
70 vmw_fences_update(dev_priv->fman); in vmw_thread_fn()
71 DRM_SPIN_WAKEUP_ALL(&dev_priv->fence_queue, in vmw_thread_fn()
72 &dev_priv->fence_lock); in vmw_thread_fn()
73 spin_unlock(&dev_priv->fence_lock); in vmw_thread_fn()
78 dev_priv->irqthread_pending)) { in vmw_thread_fn()
79 vmw_cmdbuf_irqthread(dev_priv->cman); in vmw_thread_fn()
[all …]
Dvmwgfx_fifo.c46 bool vmw_fifo_have_3d(struct vmw_private *dev_priv) in vmw_fifo_have_3d() argument
48 u32 *fifo_mem = dev_priv->mmio_virt; in vmw_fifo_have_3d()
50 const struct vmw_fifo_state *fifo = &dev_priv->fifo; in vmw_fifo_have_3d()
52 if (!(dev_priv->capabilities & SVGA_CAP_3D)) in vmw_fifo_have_3d()
55 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { in vmw_fifo_have_3d()
58 if (!dev_priv->has_mob) in vmw_fifo_have_3d()
61 spin_lock(&dev_priv->cap_lock); in vmw_fifo_have_3d()
62 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); in vmw_fifo_have_3d()
63 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); in vmw_fifo_have_3d()
64 spin_unlock(&dev_priv->cap_lock); in vmw_fifo_have_3d()
[all …]
/netbsd/src/sys/external/bsd/drm/dist/shared-core/
Dradeon_cp.c45 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
47 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr) in RADEON_READ_MM() argument
52 ret = DRM_READ32( dev_priv->mmio, addr ); in RADEON_READ_MM()
54 DRM_WRITE32( dev_priv->mmio, RADEON_MM_INDEX, addr ); in RADEON_READ_MM()
55 ret = DRM_READ32( dev_priv->mmio, RADEON_MM_DATA ); in RADEON_READ_MM()
61 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in R500_READ_MCIND() argument
70 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS480_READ_MCIND() argument
79 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS690_READ_MCIND() argument
88 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS600_READ_MCIND() argument
97 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in IGP_READ_MCIND() argument
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Dsavage_bci.c38 savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) in savage_bci_wait_fifo_shadow() argument
40 uint32_t mask = dev_priv->status_used_mask; in savage_bci_wait_fifo_shadow()
41 uint32_t threshold = dev_priv->bci_threshold_hi; in savage_bci_wait_fifo_shadow()
46 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) in savage_bci_wait_fifo_shadow()
53 status = dev_priv->status_ptr[0]; in savage_bci_wait_fifo_shadow()
67 savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) in savage_bci_wait_fifo_s3d() argument
69 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s3d()
88 savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) in savage_bci_wait_fifo_s4() argument
90 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s4()
120 savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) in savage_bci_wait_event_shadow() argument
[all …]
Di915_suspend.c37 struct drm_i915_private *dev_priv = dev->dev_private; in i915_pipe_enabled() local
47 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_palette() local
56 array = dev_priv->save_palette_a; in i915_save_palette()
58 array = dev_priv->save_palette_b; in i915_save_palette()
66 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_palette() local
75 array = dev_priv->save_palette_a; in i915_restore_palette()
77 array = dev_priv->save_palette_b; in i915_restore_palette()
85 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_indexed() local
93 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_ar() local
102 struct drm_i915_private *dev_priv = dev->dev_private; in i915_write_ar() local
[all …]
Dr600_cp.c75 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) in r600_do_wait_for_fifo() argument
79 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_fifo()
81 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_fifo()
83 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_fifo()
100 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) in r600_do_wait_for_idle() argument
104 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_idle()
106 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_idle()
107 ret = r600_do_wait_for_fifo(dev_priv, 8); in r600_do_wait_for_idle()
109 ret = r600_do_wait_for_fifo(dev_priv, 16); in r600_do_wait_for_idle()
112 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_idle()
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Dr128_cce.c86 drm_r128_private_t *dev_priv = dev->dev_private; in R128_READ_PLL() local
93 static void r128_status(drm_r128_private_t * dev_priv) in r128_status() argument
114 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv) in r128_do_pixcache_flush() argument
122 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_pixcache_flush()
135 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) in r128_do_wait_for_fifo() argument
139 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_fifo()
152 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) in r128_do_wait_for_idle() argument
156 ret = r128_do_wait_for_fifo(dev_priv, 64); in r128_do_wait_for_idle()
160 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_idle()
162 r128_do_pixcache_flush(dev_priv); in r128_do_wait_for_idle()
[all …]
Dmga_dma.c55 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) in mga_do_wait_for_idle() argument
61 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_wait_for_idle()
77 static int mga_do_dma_reset(drm_mga_private_t * dev_priv) in mga_do_dma_reset() argument
79 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_reset()
80 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
105 void mga_do_dma_flush(drm_mga_private_t * dev_priv) in mga_do_dma_flush() argument
107 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
115 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_dma_flush()
127 tail = primary->tail + dev_priv->primary->offset; in mga_do_dma_flush()
151 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); in mga_do_dma_flush()
[all …]
Di915_irq.c54 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) in i915_enable_irq() argument
57 dev_priv->irq_mask_reg, mask); in i915_enable_irq()
59 if ((dev_priv->irq_mask_reg & mask) != 0) { in i915_enable_irq()
60 dev_priv->irq_mask_reg &= ~mask; in i915_enable_irq()
61 I915_WRITE(IMR, dev_priv->irq_mask_reg); in i915_enable_irq()
67 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) in i915_disable_irq() argument
70 if ((dev_priv->irq_mask_reg & mask) != mask) { in i915_disable_irq()
71 dev_priv->irq_mask_reg |= mask; in i915_disable_irq()
72 I915_WRITE(IMR, dev_priv->irq_mask_reg); in i915_disable_irq()
88 i915_enable_pipestat(drm_i915_private_t *dev_priv, unsigned int pipe, u32 mask) in i915_enable_pipestat() argument
[all …]
Di915_dma.c41 drm_i915_private_t *dev_priv = dev->dev_private; in i915_wait_ring() local
42 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); in i915_wait_ring()
58 if (dev_priv->sarea_priv) in i915_wait_ring()
59 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; in i915_wait_ring()
81 drm_i915_private_t *dev_priv = dev->dev_private; in i915_init_phys_hws() local
85 dev_priv->status_page_dmah = in i915_init_phys_hws()
88 if (!dev_priv->status_page_dmah) { in i915_init_phys_hws()
92 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; in i915_init_phys_hws()
93 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; in i915_init_phys_hws()
95 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); in i915_init_phys_hws()
[all …]
Dmach64_dma.c60 int mach64_do_wait_for_fifo(drm_mach64_private_t *dev_priv, int entries) in mach64_do_wait_for_fifo() argument
64 for (i = 0; i < dev_priv->usec_timeout; i++) { in mach64_do_wait_for_fifo()
78 int mach64_do_wait_for_idle(drm_mach64_private_t *dev_priv) in mach64_do_wait_for_idle() argument
82 ret = mach64_do_wait_for_fifo(dev_priv, 16); in mach64_do_wait_for_idle()
86 for (i = 0; i < dev_priv->usec_timeout; i++) { in mach64_do_wait_for_idle()
93 mach64_dump_ring_info(dev_priv); in mach64_do_wait_for_idle()
116 int mach64_wait_ring(drm_mach64_private_t *dev_priv, int n) in mach64_wait_ring() argument
118 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; in mach64_wait_ring()
121 for (i = 0; i < dev_priv->usec_timeout; i++) { in mach64_wait_ring()
122 mach64_update_ring_snapshot(dev_priv); in mach64_wait_ring()
[all …]
Dradeon_irq.c40 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_irq_set_state() local
43 dev_priv->irq_enable_reg |= mask; in radeon_irq_set_state()
45 dev_priv->irq_enable_reg &= ~mask; in radeon_irq_set_state()
48 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); in radeon_irq_set_state()
53 drm_radeon_private_t *dev_priv = dev->dev_private; in r500_vbl_irq_set_state() local
56 dev_priv->r500_disp_irq_reg |= mask; in r500_vbl_irq_set_state()
58 dev_priv->r500_disp_irq_reg &= ~mask; in r500_vbl_irq_set_state()
61 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); in r500_vbl_irq_set_state()
66 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_enable_vblank() local
68 if (!dev_priv->mmio) in radeon_enable_vblank()
[all …]
/netbsd/src/sys/external/bsd/drm2/dist/drm/savage/
Dsavage_bci.c52 savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_shadow() argument
54 uint32_t mask = dev_priv->status_used_mask; in savage_bci_wait_fifo_shadow()
55 uint32_t threshold = dev_priv->bci_threshold_hi; in savage_bci_wait_fifo_shadow()
60 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) in savage_bci_wait_fifo_shadow()
67 status = dev_priv->status_ptr[0]; in savage_bci_wait_fifo_shadow()
81 savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s3d() argument
83 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s3d()
102 savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s4() argument
104 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s4()
134 savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) in savage_bci_wait_event_shadow() argument
[all …]
/netbsd/src/sys/external/bsd/drm2/dist/drm/via/
Dvia_dma.c72 dev_priv->dma_low += 8; \
80 dev_priv->dma_low += 8; \
83 static void via_cmdbuf_start(drm_via_private_t *dev_priv);
84 static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
85 static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
86 static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);
87 static int via_wait_idle(drm_via_private_t *dev_priv);
88 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
94 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv) in via_cmdbuf_space() argument
96 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; in via_cmdbuf_space()
[all …]
Dvia_irq.c100 drm_via_private_t *dev_priv = dev->dev_private; in via_get_vblank_counter() local
105 return atomic_read(&dev_priv->vbl_received); in via_get_vblank_counter()
111 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; in via_driver_irq_handler() local
115 drm_via_irq_t *cur_irq = dev_priv->via_irqs; in via_driver_irq_handler()
118 status = via_read(dev_priv, VIA_REG_INTERRUPT); in via_driver_irq_handler()
120 atomic_inc(&dev_priv->vbl_received); in via_driver_irq_handler()
121 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { in via_driver_irq_handler()
123 if (dev_priv->last_vblank_valid) { in via_driver_irq_handler()
124 dev_priv->nsec_per_vblank = in via_driver_irq_handler()
126 dev_priv->last_vblank) >> 4; in via_driver_irq_handler()
[all …]
/netbsd/src/sys/external/bsd/drm2/dist/drm/i915/
Dintel_pch.c16 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) in intel_pch_type() argument
20 drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n"); in intel_pch_type()
21 WARN_ON(!IS_GEN(dev_priv, 5)); in intel_pch_type()
24 drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n"); in intel_pch_type()
25 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
28 drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n"); in intel_pch_type()
29 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
33 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n"); in intel_pch_type()
34 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
35 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
[all …]
Di915_irq.c263 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update_locked() argument
269 lockdep_assert_held(&dev_priv->irq_lock); in i915_hotplug_interrupt_update_locked()
290 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update() argument
294 spin_lock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
295 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); in i915_hotplug_interrupt_update()
296 spin_unlock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
305 void ilk_update_display_irq(struct drm_i915_private *dev_priv, in ilk_update_display_irq() argument
311 lockdep_assert_held(&dev_priv->irq_lock); in ilk_update_display_irq()
315 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ilk_update_display_irq()
318 new_val = dev_priv->irq_mask; in ilk_update_display_irq()
[all …]
Di915_drv.h197 struct drm_i915_private *dev_priv; member
270 void (*get_cdclk)(struct drm_i915_private *dev_priv,
272 void (*set_cdclk)(struct drm_i915_private *dev_priv,
275 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
311 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
312 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
537 struct drm_i915_private *dev_priv; member
1407 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) argument
1408 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) argument
1409 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) argument
[all …]
Di915_drv.c167 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) in i915_get_bridge_dev() argument
169 int domain = pci_domain_nr(dev_priv->drm.pdev->bus); in i915_get_bridge_dev()
171 dev_priv->bridge_dev = in i915_get_bridge_dev()
173 if (!dev_priv->bridge_dev) { in i915_get_bridge_dev()
182 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) in intel_alloc_mchbar_resource() argument
184 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
192 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource()
193 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); in intel_alloc_mchbar_resource()
194 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); in intel_alloc_mchbar_resource()
204 dev_priv->mch_res.name = "i915 MCHBAR"; in intel_alloc_mchbar_resource()
[all …]
Di915_suspend.c42 static void i915_save_display(struct drm_i915_private *dev_priv) in i915_save_display() argument
45 if (INTEL_GEN(dev_priv) <= 4) in i915_save_display()
46 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
49 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_save_display()
50 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); in i915_save_display()
53 static void i915_restore_display(struct drm_i915_private *dev_priv) in i915_restore_display() argument
56 if (INTEL_GEN(dev_priv) <= 4) in i915_restore_display()
57 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()
60 intel_fbc_global_disable(dev_priv); in i915_restore_display()
63 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_restore_display()
[all …]
Dintel_pch.h59 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
60 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) argument
61 #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) argument
62 #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) argument
63 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) argument
64 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
65 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
66 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) argument
67 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) argument
68 #define HAS_PCH_LPT_LP(dev_priv) \ argument
[all …]
Dintel_pm.c58 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) in gen9_init_clock_gating() argument
60 if (HAS_LLC(dev_priv)) { in gen9_init_clock_gating()
91 if (IS_SKYLAKE(dev_priv)) { in gen9_init_clock_gating()
98 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) in bxt_init_clock_gating() argument
100 gen9_init_clock_gating(dev_priv); in bxt_init_clock_gating()
129 static void glk_init_clock_gating(struct drm_i915_private *dev_priv) in glk_init_clock_gating() argument
131 gen9_init_clock_gating(dev_priv); in glk_init_clock_gating()
142 if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) { in glk_init_clock_gating()
152 static void pnv_get_mem_freq(struct drm_i915_private *dev_priv) in pnv_get_mem_freq() argument
160 dev_priv->fsb_freq = 533; /* 133*4 */ in pnv_get_mem_freq()
[all …]
/netbsd/src/sys/external/bsd/drm2/dist/drm/r128/
Dr128_cce.c62 drm_r128_private_t *dev_priv = dev->dev_private; in R128_READ_PLL() local
69 static void r128_status(drm_r128_private_t *dev_priv) in r128_status() argument
90 static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv) in r128_do_pixcache_flush() argument
98 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_pixcache_flush()
110 static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries) in r128_do_wait_for_fifo() argument
114 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_fifo()
127 static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv) in r128_do_wait_for_idle() argument
131 ret = r128_do_wait_for_fifo(dev_priv, 64); in r128_do_wait_for_idle()
135 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_idle()
137 r128_do_pixcache_flush(dev_priv); in r128_do_wait_for_idle()
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/netbsd/src/sys/external/bsd/drm2/dist/drm/mga/
Dmga_dma.c58 int mga_do_wait_for_idle(drm_mga_private_t *dev_priv) in mga_do_wait_for_idle() argument
64 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_wait_for_idle()
80 static int mga_do_dma_reset(drm_mga_private_t *dev_priv) in mga_do_dma_reset() argument
82 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_reset()
83 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
108 void mga_do_dma_flush(drm_mga_private_t *dev_priv) in mga_do_dma_flush() argument
110 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
118 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_dma_flush()
130 tail = primary->tail + dev_priv->primary->offset; in mga_do_dma_flush()
153 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); in mga_do_dma_flush()
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