1 /* $NetBSD: amrreg.h,v 1.6 2023/08/15 04:04:10 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999,2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * from FreeBSD: amrreg.h,v 1.2 2000/08/30 07:52:40 msmith Exp 59 */ 60 61 #ifndef _PCI_AMRREG_H_ 62 #define _PCI_AMRREG_H_ 63 64 #ifdef AMR_CRASH_ME 65 #define AMR_MAX_CMDS 255 /* ident = 0 not allowed */ 66 #else 67 #define AMR_MAX_CMDS 120 68 #endif 69 #define AMR_MAXLD 40 70 71 #define AMR_MAX_CMDS_PU 63 72 73 #define AMR_MAX_SEGS 26 74 #define AMR_MAX_CHANNEL 3 75 #define AMR_MAX_TARGET 15 76 #define AMR_MAX_LUN 7 77 78 #define AMR_MAX_CDB_LEN 0x0a 79 #define AMR_MAX_REQ_SENSE_LEN 0x20 80 81 #define AMR_SECTOR_SIZE 512 82 83 /* Mailbox commands.*/ 84 #define AMR_CMD_LREAD 0x01 85 #define AMR_CMD_LWRITE 0x02 86 #define AMR_CMD_PASS 0x03 87 #define AMR_CMD_EXT_ENQUIRY 0x04 88 #define AMR_CMD_ENQUIRY 0x05 89 #define AMR_CMD_FLUSH 0x0a 90 #define AMR_CMD_EXT_ENQUIRY2 0x0c 91 #define AMR_CMD_GET_MACHINEID 0x36 92 #define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 93 #define AMR_CMD_CONFIG 0xa1 94 #define AMR_CONFIG_PRODUCT_INFO 0x0e 95 #define AMR_CONFIG_ENQ3 0x0f 96 #define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 97 #define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 98 #define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 99 100 /* Command completion status. */ 101 #define AMR_STATUS_SUCCESS 0x00 102 #define AMR_STATUS_ABORTED 0x02 103 #define AMR_STATUS_FAILED 0x80 104 105 /* Physical/logical drive states. */ 106 #define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 107 #define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 108 #define AMR_DRV_OFFLINE 0x00 109 #define AMR_DRV_DEGRADED 0x01 110 #define AMR_DRV_OPTIMAL 0x02 111 #define AMR_DRV_ONLINE 0x03 112 #define AMR_DRV_FAILED 0x04 113 #define AMR_DRV_REBUILD 0x05 114 #define AMR_DRV_HOTSPARE 0x06 115 116 /* Logical drive properties. */ 117 #define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 118 #define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 119 #define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 120 #define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 121 122 /* Battery status. */ 123 #define AMR_BATT_MODULE_MISSING 0x01 124 #define AMR_BATT_LOW_VOLTAGE 0x02 125 #define AMR_BATT_TEMP_HIGH 0x04 126 #define AMR_BATT_PACK_MISSING 0x08 127 #define AMR_BATT_CHARGE_MASK 0x30 128 #define AMR_BATT_CHARGE_DONE 0x00 129 #define AMR_BATT_CHARGE_INPROG 0x10 130 #define AMR_BATT_CHARGE_FAIL 0x20 131 #define AMR_BATT_CYCLES_EXCEEDED 0x40 132 133 /* 134 * 8LD firmware interface. 135 */ 136 137 /* Array constraints. */ 138 #define AMR_8LD_MAXDRIVES 8 139 #define AMR_8LD_MAXCHAN 5 140 #define AMR_8LD_MAXTARG 15 141 #define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 142 143 /* Adapter information. */ 144 struct amr_adapter_info { 145 u_int8_t aa_maxio; 146 u_int8_t aa_rebuild_rate; 147 u_int8_t aa_maxtargchan; 148 u_int8_t aa_channels; 149 u_int8_t aa_firmware[4]; 150 u_int16_t aa_flashage; 151 u_int8_t aa_chipsetvalue; 152 u_int8_t aa_memorysize; 153 u_int8_t aa_cacheflush; 154 u_int8_t aa_bios[4]; 155 u_int8_t aa_boardtype; 156 u_int8_t aa_scsisensealert; 157 u_int8_t aa_writeconfigcount; 158 u_int8_t aa_driveinsertioncount; 159 u_int8_t aa_inserteddrive; 160 u_int8_t aa_batterystatus; 161 u_int8_t aa_res1; 162 } __packed; 163 164 /* Logical drive information. */ 165 struct amr_logdrive_info { 166 u_int8_t al_numdrives; 167 u_int8_t al_res1[3]; 168 u_int32_t al_size[AMR_8LD_MAXDRIVES]; 169 u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 170 u_int8_t al_state[AMR_8LD_MAXDRIVES]; 171 } __packed; 172 173 /* Physical drive information. */ 174 struct amr_physdrive_info { 175 /* Low nybble is current state, high nybble is previous state. */ 176 u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; 177 u_int8_t ap_predictivefailure; 178 } __packed; 179 180 /* 181 * Enquiry response structure for AMR_CMD_ENQUIRY (e), AMR_CMD_EXT_ENQUIRY (x) 182 * and AMR_CMD_EXT_ENQUIRY2 (2). 183 */ 184 struct amr_enquiry { 185 struct amr_adapter_info ae_adapter; /* e x 2 */ 186 struct amr_logdrive_info ae_ldrv; /* e x 2 */ 187 struct amr_physdrive_info ae_pdrv; /* e x 2 */ 188 u_int8_t ae_formatting[AMR_8LD_MAXDRIVES]; /* x 2 */ 189 u_int8_t res1[AMR_8LD_MAXDRIVES]; /* x 2 */ 190 u_int32_t ae_extlen; /* 2 */ 191 u_int16_t ae_subsystem; /* 2 */ 192 u_int16_t ae_subvendor; /* 2 */ 193 u_int32_t ae_signature; /* 2 */ 194 #define AMR_SIG_431 0xfffe0001 195 #define AMR_SIG_438 0xfffd0002 196 #define AMR_SIG_762 0xfffc0003 197 #define AMR_SIG_T5 0xfffb0004 198 #define AMR_SIG_466 0xfffa0005 199 #define AMR_SIG_467 0xfff90006 200 #define AMR_SIG_T7 0xfff80007 201 #define AMR_SIG_490 0xfff70008 202 u_int8_t res2[844]; /* 2 */ 203 } __packed; 204 205 /* 206 * 40LD firmware interface. 207 */ 208 209 /* Array constraints. */ 210 #define AMR_40LD_MAXDRIVES 40 211 #define AMR_40LD_MAXCHAN 16 212 #define AMR_40LD_MAXTARG 16 213 #define AMR_40LD_MAXPHYSDRIVES 256 214 215 /* Product information structure. */ 216 struct amr_prodinfo { 217 u_int32_t ap_size; /* current size in bytes (not including resvd) */ 218 u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 219 * logical drives, 0x20 maximum stripes and 0x08 220 * maximum spans */ 221 u_int8_t ap_firmware[16]; /* printable identifiers */ 222 u_int8_t ap_bios[16]; 223 u_int8_t ap_product[80]; 224 u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 225 u_int8_t ap_nschan; /* number of SCSI channels present */ 226 u_int8_t ap_fcloops; /* number of fibre loops present */ 227 u_int8_t ap_memtype; /* memory type */ 228 u_int32_t ap_signature; 229 u_int16_t ap_memsize; /* onboard memory in MB */ 230 u_int16_t ap_subsystem; /* subsystem identifier */ 231 u_int16_t ap_subvendor; /* subsystem vendor ID */ 232 u_int8_t ap_numnotifyctr; /* number of notify counters */ 233 } __packed; 234 235 /* Notify structure. */ 236 struct amr_notify { 237 u_int32_t an_globalcounter; /* change counter */ 238 239 u_int8_t an_paramcounter; /* parameter change counter */ 240 u_int8_t an_paramid; 241 #define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 242 #define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 243 #define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 244 #define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 245 #define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 246 u_int16_t an_paramval; 247 248 u_int8_t an_writeconfigcounter; /* write config occurred */ 249 u_int8_t res1[3]; 250 251 u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 252 u_int8_t an_ldrvopid; 253 u_int8_t an_ldrvopcmd; 254 #define AMR_LDRVOP_CHECK 0x01 255 #define AMR_LDRVOP_INIT 0x02 256 #define AMR_LDRVOP_REBUILD 0x03 257 u_int8_t an_ldrvopstatus; 258 #define AMR_LDRVOP_SUCCESS 0x00 259 #define AMR_LDRVOP_FAILED 0x01 260 #define AMR_LDRVOP_ABORTED 0x02 261 #define AMR_LDRVOP_CORRECTED 0x03 262 #define AMR_LDRVOP_STARTED 0x04 263 264 u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 265 u_int8_t an_ldrvstateid; 266 u_int8_t an_ldrvstatenew; 267 u_int8_t an_ldrvstateold; 268 269 u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 270 u_int8_t an_pdrvstateid; 271 u_int8_t an_pdrvstatenew; 272 u_int8_t an_pdrvstateold; 273 274 u_int8_t an_pdrvfmtcounter; 275 u_int8_t an_pdrvfmtid; 276 u_int8_t an_pdrvfmtval; 277 #define AMR_FORMAT_START 0x01 278 #define AMR_FORMAT_COMPLETE 0x02 279 u_int8_t res2; 280 281 u_int8_t an_targxfercounter; /* scsi xfer rate change */ 282 u_int8_t an_targxferid; 283 u_int8_t an_targxferval; 284 u_int8_t res3; 285 286 u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 287 u_int8_t an_fcloopidpdrvid; 288 u_int8_t an_fcloopid0; 289 u_int8_t an_fcloopid1; 290 291 u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 292 u_int8_t an_fcloopstate0; 293 u_int8_t an_fcloopstate1; 294 u_int8_t res4; 295 } __packed; 296 297 /* Enquiry3 structure. */ 298 struct amr_enquiry3 { 299 u_int32_t ae_datasize; /* valid data size in this structure */ 300 union { /* event notify structure */ 301 struct amr_notify n; 302 u_int8_t pad[0x80]; 303 } ae_notify; 304 u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 305 u_int8_t ae_cacheflush; /* flush interval in seconds */ 306 u_int8_t ae_sensealert; 307 u_int8_t ae_driveinsertcount; /* count of inserted drives */ 308 u_int8_t ae_batterystatus; 309 u_int8_t ae_numldrives; 310 u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 311 u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 312 u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 313 u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 314 u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */ 315 u_int8_t ae_pdrivestate[AMR_40LD_MAXPHYSDRIVES]; /* physical drive state */ 316 u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES / 16]; 317 u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 318 319 u_int8_t res1[263]; /* pad to 1024 bytes */ 320 } __packed; 321 322 /* 323 * Mailbox and command structures. 324 */ 325 326 struct amr_mailbox_cmd { 327 u_int8_t mb_command; 328 u_int8_t mb_ident; 329 u_int16_t mb_blkcount; 330 u_int32_t mb_lba; 331 u_int32_t mb_physaddr; 332 u_int8_t mb_drive; 333 u_int8_t mb_nsgelem; 334 u_int8_t res1; 335 u_int8_t mb_busy; 336 } __packed; 337 338 struct amr_mailbox_resp { 339 u_int8_t mb_nstatus; 340 u_int8_t mb_status; 341 u_int8_t mb_completed[46]; 342 } __packed; 343 344 struct amr_mailbox { 345 u_int32_t mb_res1[3]; 346 u_int32_t mb_segment; 347 struct amr_mailbox_cmd mb_cmd; 348 struct amr_mailbox_resp mb_resp; 349 u_int8_t mb_poll; 350 u_int8_t mb_ack; 351 u_int8_t res2[62]; /* Pad to 128+16 bytes. */ 352 } __packed; 353 354 struct amr_mailbox_ioctl { 355 u_int8_t mb_command; 356 u_int8_t mb_ident; 357 u_int8_t mb_channel; 358 u_int8_t mb_param; 359 u_int8_t mb_pad[4]; 360 u_int32_t mb_physaddr; 361 u_int8_t mb_drive; 362 u_int8_t mb_nsgelem; 363 u_int8_t res1; 364 u_int8_t mb_busy; 365 u_int8_t mb_nstatus; 366 u_int8_t mb_completed[46]; 367 u_int8_t mb_poll; 368 u_int8_t mb_ack; 369 u_int8_t res4[16]; 370 } __packed; 371 372 struct amr_sgentry { 373 u_int32_t sge_addr; 374 u_int32_t sge_count; 375 } __packed; 376 377 struct amr_passthrough { 378 u_int8_t ap_timeout:3; 379 u_int8_t ap_ars:1; 380 u_int8_t ap_dummy:3; 381 u_int8_t ap_islogical:1; 382 u_int8_t ap_logical_drive_no; 383 u_int8_t ap_channel; 384 u_int8_t ap_scsi_id; 385 u_int8_t ap_queue_tag; 386 u_int8_t ap_queue_action; 387 u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 388 u_int8_t ap_cdb_length; 389 u_int8_t ap_request_sense_length; 390 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 391 u_int8_t ap_no_sg_elements; 392 u_int8_t ap_scsi_status; 393 u_int32_t ap_data_transfer_address; 394 u_int32_t ap_data_transfer_length; 395 } __packed; 396 397 /* 398 * "Quartz" i960 PCI bridge interface. 399 */ 400 401 #define AMR_QUARTZ_SIG_REG 0xa0 402 #define AMR_QUARTZ_SIG0 0xcccc 403 #define AMR_QUARTZ_SIG1 0x3344 404 405 /* Doorbell registers. */ 406 #define AMR_QREG_IDB 0x20 407 #define AMR_QREG_ODB 0x2c 408 409 #define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 410 #define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 411 #define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 412 413 /* 414 * Old-style ("standard") ASIC bridge interface. 415 */ 416 417 /* I/O registers. */ 418 #define AMR_SREG_CMD 0x10 /* Command/ack register (w) */ 419 #define AMR_SREG_MBOX_BUSY 0x10 /* Mailbox status (r) */ 420 #define AMR_SREG_TOGL 0x11 /* Interrupt enable */ 421 #define AMR_SREG_MBOX 0x14 /* Mailbox physical address */ 422 #define AMR_SREG_MBOX_ENABLE 0x18 /* Atomic mailbox address enable */ 423 #define AMR_SREG_INTR 0x1a /* Interrupt status */ 424 425 /* I/O magic numbers. */ 426 #define AMR_SCMD_POST 0x10 /* in SCMD to initiate action on mailbox */ 427 #define AMR_SCMD_ACKINTR 0x08 /* in SCMD to ack mailbox retrieved */ 428 #define AMR_STOGL_ENABLE 0xc0 /* in STOGL */ 429 #define AMR_SINTR_VALID 0x40 /* in SINTR */ 430 #define AMR_SMBOX_BUSY_FLAG 0x10 /* in SMBOX_BUSY */ 431 #define AMR_SMBOX_ENABLE_ADDR 0x00 /* in SMBOX_ENABLE */ 432 433 #endif /* !_PCI_AMRREG_H_ */ 434