1 /* $NetBSD: schizoreg.h,v 1.12 2018/10/19 21:47:03 macallan Exp $ */ 2 /* $OpenBSD: schizoreg.h,v 1.20 2008/07/12 13:08:04 kettenis Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 6 * Copyright (c) 2010 Matthew R. Green 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 struct schizo_pbm_regs { 32 volatile u_int64_t _unused1[64]; /* 0x0000 - 0x01ff */ 33 struct iommureg2 iommu; /* 0x0200 - 0x03ff */ 34 volatile u_int64_t _unused2[384]; 35 volatile u_int64_t imap[64]; /* 0x1000 - 0x11ff */ 36 volatile u_int64_t _unused3[64]; 37 volatile u_int64_t iclr[64]; /* 0x1400 - 0x15ff */ 38 volatile u_int64_t _unused4_0[64]; 39 volatile u_int64_t _unused4_1[64]; /* 0x1800 - 0x19ff */ 40 volatile u_int64_t intr_retry; /* 0x1a00 */ 41 volatile u_int64_t _unused4_2; 42 volatile u_int64_t dma_flushsync_compl; /* 0x1a10 */ 43 volatile u_int64_t dma_flushsync_pend; /* 0x1a18 */ 44 volatile u_int64_t _unused4_3[60]; 45 volatile u_int64_t _unused4_4[64]; 46 volatile u_int64_t _unused4_5[64]; 47 volatile u_int64_t ctrl; 48 volatile u_int64_t __unused0; 49 volatile u_int64_t afsr; 50 volatile u_int64_t afar; 51 volatile u_int64_t _unused11[68]; 52 volatile u_int64_t int_routing; 53 volatile u_int64_t _unused5[183]; 54 struct iommu_strbuf strbuf; 55 volatile u_int64_t strbuf_ctxflush; 56 volatile u_int64_t _unused6[4012]; 57 volatile u_int64_t iommu_tag; 58 volatile u_int64_t _unused7[15]; 59 volatile u_int64_t iommu_data; 60 volatile u_int64_t _unused8[63]; 61 volatile u_int64_t istat[2]; 62 volatile u_int64_t _unused9[2814]; 63 volatile u_int64_t strbuf_ctxmatch; 64 volatile u_int64_t _unused10[122879]; 65 }; 66 67 struct schizo_regs { 68 volatile u_int64_t _unused0[8]; 69 volatile u_int64_t pcia_mem_match; 70 volatile u_int64_t pcia_mem_mask; 71 volatile u_int64_t pcia_io_match; 72 volatile u_int64_t pcia_io_mask; 73 volatile u_int64_t pcib_mem_match; 74 volatile u_int64_t pcib_mem_mask; 75 volatile u_int64_t pcib_io_match; 76 volatile u_int64_t pcib_io_mask; 77 volatile u_int64_t _unused1[8176]; 78 79 volatile u_int64_t control_status; 80 volatile u_int64_t error_control; 81 volatile u_int64_t interrupt_control; 82 volatile u_int64_t safari_errlog; 83 volatile u_int64_t eccctrl; 84 volatile u_int64_t _unused3[1]; 85 volatile u_int64_t ue_afsr; 86 volatile u_int64_t ue_afar; 87 volatile u_int64_t ce_afsr; 88 volatile u_int64_t ce_afar; 89 90 volatile u_int64_t _unused4[253942]; 91 struct schizo_pbm_regs pbm_a; 92 struct schizo_pbm_regs pbm_b; 93 }; 94 95 #define SCZ_PCIA_MEM_MATCH 0x00040 96 #define SCZ_PCIA_MEM_MASK 0x00048 97 #define SCZ_PCIA_IO_MATCH 0x00050 98 #define SCZ_PCIA_IO_MASK 0x00058 99 #define SCZ_PCIB_MEM_MATCH 0x00060 100 #define SCZ_PCIB_MEM_MASK 0x00068 101 #define SCZ_PCIB_IO_MATCH 0x00070 102 #define SCZ_PCIB_IO_MASK 0x00078 103 104 #define SCZ_CONTROL_STATUS 0x10000 105 # define SCZ_CONTROL_STATUS_AID_MASK 0x1f00000 106 # define SCZ_CONTROL_STATUS_AID_SHIFT 20 107 #define SCZ_SAFARI_INTCTRL 0x10010 108 #define SCZ_SAFARI_ERRLOG 0x10018 109 #define SCZ_ECCCTRL 0x10020 110 #define SCZ_UE_AFSR 0x10030 111 #define SCZ_UE_AFAR 0x10038 112 #define SCZ_CE_AFSR 0x10040 113 #define SCZ_CE_AFAR 0x10048 114 #define SCZ_JBUS_ESTAR 0x10050 115 #define SCZ_JBUS_CHANGE_INIT 0x10058 116 117 #define SCZ_JBUS_GPIO_0 0x60000 /* 8bit */ 118 #define SCZ_JBUS_GPIO_1 0x60001 /* 8bit */ 119 #define SCZ_JBUS_GPIO_2 0x62000 /* 8bit */ 120 #define SCZ_JBUS_GPIO_3 0x62001 /* 8bit */ 121 #define SCZ_JBUS_GPIO_DATA 0x64000 /* 64bit, data in lower 4 */ 122 #define SCZ_JBUS_GPIO_DIR 0x64008 /* 1 - output, 0 - input */ 123 124 125 /* These are relative to the PBM */ 126 #define SCZ_PCI_IOMMU_CTRL 0x00200 127 #define SCZ_PCI_IOMMU_TSBBASE 0x00208 128 #define SCZ_PCI_IOMMU_FLUSH 0x00210 129 #define SCZ_PCI_IOMMU_CTXFLUSH 0x00218 130 #define TOM_PCI_IOMMU_TFAR 0x00220 131 #define SCZ_PCI_IMAP_BASE 0x01000 132 #define SCZ_PCI_ICLR_BASE 0x01400 133 #define SCZ_PCI_INTR_RETRY 0x01a00 /* interrupt retry */ 134 #define SCZ_PCI_DMA_FLUSH 0x01a08 /* pci consistent dma flush */ 135 #define TOM_PCI_DMA_FLUSH_COMPLETE 0x01a10 /* diag */ 136 #define TOM_PCI_DMA_FLUSH_PENDING 0x01a18 /* Tomatillo version */ 137 #define SCZ_PCI_CTRL 0x02000 138 #define SCZ_PCI_AFSR 0x02010 139 #define SCZ_PCI_AFAR 0x02018 140 #define SCZ_PCI_DIAG 0x02020 141 #define SCZ_PCI_ESTAR 0x02028 142 #define SCZ_PCI_IOCACHE_CSR 0x02248 143 #define SCZ_PCI_IOCACHE_TAG_DIAG_BASE 0x02250 144 #define SCZ_PCI_IOCACHE_TAG_DATA_BASE 0x02290 145 #define SCZ_PCI_STRBUF_CTRL 0x02800 146 #define SCZ_PCI_STRBUF_FLUSH 0x02808 147 #define SCZ_PCI_STRBUF_FSYNC 0x02810 148 #define SCZ_PCI_STRBUF_CTXFLUSH 0x02818 149 #define SCZ_PCI_IOMMU_TAG 0x0a580 150 #define SCZ_PCI_IOMMU_DATA 0x0a600 151 #define SCZ_PCI_STRBUF_CTXMATCH 0x10000 152 153 #define SCZ_ECCCTRL_EE_INTEN 0x8000000000000000UL 154 #define SCZ_ECCCTRL_UE_INTEN 0x4000000000000000UL 155 #define SCZ_ECCCTRL_CE_INTEN 0x2000000000000000UL 156 157 #define SCZ_UEAFSR_PPIO 0x8000000000000000UL 158 #define SCZ_UEAFSR_PDRD 0x4000000000000000UL 159 #define SCZ_UEAFSR_PDWR 0x2000000000000000UL 160 #define SCZ_UEAFSR_SPIO 0x1000000000000000UL 161 #define SCZ_UEAFSR_SDMA 0x0800000000000000UL 162 #define SCZ_UEAFSR_ERRPNDG 0x0300000000000000UL 163 #define SCZ_UEAFSR_BMSK 0x000003ff00000000UL 164 #define SCZ_UEAFSR_QOFF 0x00000000c0000000UL 165 #define SCZ_UEAFSR_AID 0x000000001f000000UL 166 #define SCZ_UEAFSR_PARTIAL 0x0000000000800000UL 167 #define SCZ_UEAFSR_OWNEDIN 0x0000000000400000UL 168 #define SCZ_UEAFSR_MTAGSYND 0x00000000000f0000UL 169 #define SCZ_UEAFSR_MTAG 0x000000000000e000UL 170 #define SCZ_UEAFSR_ECCSYND 0x00000000000001ffUL 171 172 #define SCZ_UEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */ 173 #define SCZ_UEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */ 174 #define SCZ_UEAFAR_PIO_UPA 0x0000078000000000UL /* upa */ 175 #define SZC_UEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */ 176 #define SCZ_UEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */ 177 #define SCZ_UEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */ 178 #define SCZ_UEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */ 179 #define SCZ_UEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */ 180 #define SCZ_UEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */ 181 #define SZC_UEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */ 182 #define SZC_UEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */ 183 #define SZC_UEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */ 184 #define SCZ_UEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */ 185 #define SCZ_UEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */ 186 187 #define SCZ_CEAFSR_PPIO 0x8000000000000000UL 188 #define SCZ_CEAFSR_PDRD 0x4000000000000000UL 189 #define SCZ_CEAFSR_PDWR 0x2000000000000000UL 190 #define SCZ_CEAFSR_SPIO 0x1000000000000000UL 191 #define SCZ_CEAFSR_SDMA 0x0800000000000000UL 192 #define SCZ_CEAFSR_ERRPNDG 0x0300000000000000UL 193 #define SCZ_CEAFSR_BMSK 0x000003ff00000000UL 194 #define SCZ_CEAFSR_QOFF 0x00000000c0000000UL 195 #define SCZ_CEAFSR_AID 0x000000001f000000UL 196 #define SCZ_CEAFSR_PARTIAL 0x0000000000800000UL 197 #define SCZ_CEAFSR_OWNEDIN 0x0000000000400000UL 198 #define SCZ_CEAFSR_MTAGSYND 0x00000000000f0000UL 199 #define SCZ_CEAFSR_MTAG 0x000000000000e000UL 200 #define SCZ_CEAFSR_ECCSYND 0x00000000000001ffUL 201 202 #define SCZ_CEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */ 203 #define SCZ_CEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */ 204 #define SCZ_CEAFAR_PIO_UPA 0x0000078000000000UL /* upa */ 205 #define SZC_CEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */ 206 #define SCZ_CEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */ 207 #define SCZ_CEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */ 208 #define SCZ_CEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */ 209 #define SCZ_CEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */ 210 #define SCZ_CEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */ 211 #define SZC_CEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */ 212 #define SZC_CEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */ 213 #define SZC_CEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */ 214 #define SCZ_CEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */ 215 #define SCZ_CEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */ 216 217 #define SCZ_PCICTRL_BUS_UNUS (1ULL << 63UL) /* bus unusable */ 218 #define TOM_PCICTRL_DTO_ERR (1ULL << 62UL) /* pci discard timeout */ 219 #define TOM_PCICTRL_DTO_INT (1ULL << 61UL) /* discard intr en */ 220 #define SCZ_PCICTRL_ESLCK (1ULL << 51UL) /* error slot locked */ 221 #define SCZ_PCICTRL_ERRSLOT (7ULL << 48UL) /* error slot */ 222 #define SCZ_PCICTRL_TTO_ERR (1ULL << 38UL) /* pci trdy# timeout */ 223 #define SCZ_PCICTRL_RTRY_ERR (1ULL << 37UL) /* pci rtry# timeout */ 224 #define SCZ_PCICTRL_MMU_ERR (1ULL << 36UL) /* pci mmu error */ 225 #define SCZ_PCICTRL_SBH_ERR (1ULL << 35UL) /* pci strm hole */ 226 #define SCZ_PCICTRL_SERR (1ULL << 34UL) /* pci serr# sampled */ 227 #define SCZ_PCICTRL_PCISPD (1ULL << 33UL) /* speed (0=clk/2,1=clk) */ 228 #define TOM_PCICTRL_PRM (1ULL << 30UL) /* prefetch read multiple */ 229 #define TOM_PCICTRL_PRO (1ULL << 29UL) /* prefetch read one */ 230 #define TOM_PCICTRL_PRL (1ULL << 28UL) /* prefetch read line */ 231 #define SCZ_PCICTRL_PTO (3UL << 24UL) /* pci timeout interval */ 232 #define SCZ_PCICTRL_MMU_INT (1UL << 19UL) /* mmu intr en */ 233 #define SCZ_PCICTRL_SBH_INT (1UL << 18UL) /* strm byte hole intr en */ 234 #define SCZ_PCICTRL_EEN (1UL << 17UL) /* error intr en */ 235 #define SCZ_PCICTRL_PARK (1UL << 16UL) /* bus parked */ 236 #define SCZ_PCICTRL_PCIRST (1UL << 8UL) /* pci reset */ 237 #define TOM_PCICTRL_ARB (0xffUL << 0UL) /* dma arb enables, tomatillo */ 238 #define SCZ_PCICTRL_ARB (0x3fUL << 0UL) /* dma arb enables */ 239 #define SCZ_PCICTRL_BITS "\20\277UNUS\276DTO\275DTO_INT\263ESLCK\246TTO\245RTRY\244MMU\243SBH\242SERR\241SPD\223MMU_INT\222SBH_INT\221EEN\220PARK\210PCIRST" 240 241 #define SCZ_PCIAFSR_PMA 0x8000000000000000UL 242 #define SCZ_PCIAFSR_PTA 0x4000000000000000UL 243 #define SCZ_PCIAFSR_PRTRY 0x2000000000000000UL 244 #define SCZ_PCIAFSR_PPERR 0x1000000000000000UL 245 #define SCZ_PCIAFSR_PTTO 0x0800000000000000UL 246 #define SCZ_PCIAFSR_PUNUS 0x0400000000000000UL 247 #define SCZ_PCIAFSR_SMA 0x0200000000000000UL 248 #define SCZ_PCIAFSR_STA 0x0100000000000000UL 249 #define SCZ_PCIAFSR_SRTRY 0x0080000000000000UL 250 #define SCZ_PCIAFSR_SPERR 0x0040000000000000UL 251 #define SCZ_PCIAFSR_STTO 0x0020000000000000UL 252 #define SCZ_PCIAFSR_SUNUS 0x0010000000000000UL 253 #define SCZ_PCIAFSR_BMSK 0x000003ff00000000UL 254 #define SCZ_PCIAFSR_BLK 0x0000000080000000UL 255 #define SCZ_PCIAFSR_CFG 0x0000000040000000UL 256 #define SCZ_PCIAFSR_MEM 0x0000000020000000UL 257 #define SCZ_PCIAFSR_IO 0x0000000010000000UL 258 259 #define SCZ_PCIAFSR_BITS "\20\277PMA\276PTA\275PRTRY\274PPERR\273PTTO\272PUNUS\271SMA\270STA\267SRTRY\266SPERR\265STTO\264SUNUS\237BLK\236CFG\235MEM\234IO" 260 261 #define SCZ_PCIDIAG_D_BADECC (1UL << 10UL) /* disable bad ecc */ 262 #define SCZ_PCIDIAG_D_BYPASS (1UL << 9UL) /* disable mmu bypass */ 263 #define SCZ_PCIDIAG_D_TTO (1UL << 8UL) /* disable trdy# timeout */ 264 #define SCZ_PCIDIAG_D_RTRYARB (1UL << 7UL) /* disable retry arb */ 265 #define SCZ_PCIDIAG_D_RETRY (1UL << 6UL) /* disable retry lim */ 266 #define SCZ_PCIDIAG_D_INTSYNC (1UL << 5UL) /* disable write sync */ 267 #define SCZ_PCIDIAG_I_DMADPAR (1UL << 3UL) /* invert dma parity */ 268 #define SCZ_PCIDIAG_I_PIODPAR (1UL << 2UL) /* invert pio data parity */ 269 #define SCZ_PCIDIAG_I_PIOAPAR (1UL << 1UL) /* invert pio addr parity */ 270 271 /* Enable prefetch bits */ 272 #define TOM_IOCACHE_CSR_WRT_PEN (1UL << 19UL) /* for partial line writes */ 273 #define TOM_IOCACHE_CSR_NCP_RDM (1UL << 18UL) /* memory read multiple (NC) */ 274 #define TOM_IOCACHE_CSR_NCP_ONE (1UL << 17UL) /* memory read (NC) */ 275 #define TOM_IOCACHE_CSR_NCP_LINE (1UL << 16UL) /* memory read line (NC) */ 276 #define TOM_IOCACHE_CSR_POFFSET_SHIFT (1UL << 3UL) /* prefetch offset */ 277 #define TOM_IOCACHE_CSR_PEN_RDM (1UL << 2UL) /* memory read multiple */ 278 #define TOM_IOCACHE_CSR_PEN_ONE (1UL << 1UL) /* memory read */ 279 #define TOM_IOCACHE_CSR_PEN_LINE (1UL << 0UL) /* memory read line */ 280 /* Prefetch lines selection 0x0 = 1, 0x3 = 4 */ 281 #define TOM_IOCACHE_CSR_PLEN_RDM_MASK 0x000000000000c000UL /* read multiple */ 282 #define TOM_IOCACHE_CSR_PLEN_RDM_SHIFT 14 283 #define TOM_IOCACHE_CSR_PLEN_ONE_MASK 0x0000000000003000UL /* read one */ 284 #define TOM_IOCACHE_CSR_PLEN_ONE_SHIFT 12 285 #define TOM_IOCACHE_CSR_PLEN_LINE_MASK 0x0000000000000c00UL /* read line */ 286 #define TOM_IOCACHE_CSR_PLEN_LINE_SHIFT 10 287 /* Prefetch offset selection 0x00 = 1, 0x7e = 127, 0x7f = invalid */ 288 #define TOM_IOCACHE_CSR_POFFSET_MASK 0x00000000000003f8UL 289 290 #define TOM_IOCACHE_CSR_BITS "\177\020" \ 291 "b\19WRT_PEN\0b\18NCP_RDM\0b17NCP_ONE\0b\16NCP_LINE\0" \ 292 "f\14\2PLEN_RDM\0f\12\2PEN_ONE\0f\10\2PEN_LINE\0" \ 293 "f\3\7POFFSET\0" \ 294 "b\2PEN_RDM\0b\1PEN_ONE\0b\0PEN_LINE\0\0" 295 296 #define TOM_IOMMU_ERR (1UL << 24) 297 #define TOM_IOMMU_ERR_MASK (3UL << 25) 298 #define TOM_IOMMU_PROT_ERR (0UL << 25) 299 #define TOM_IOMMU_INV_ERR (1UL << 25) 300 #define TOM_IOMMU_TO_ERR (2UL << 25) 301 #define TOM_IOMMU_ECC_ERR (3UL << 25) 302 #define TOM_IOMMU_ILLTSBTBW_ERR (1UL << 27) 303 #define TOM_IOMMU_BADVA_ERR (1UL << 28) 304 305 #define SCZ_PBM_A_REGS (0x600000UL - 0x400000UL) 306 #define SCZ_PBM_B_REGS (0x700000UL - 0x400000UL) 307 308 #define SCZ_UE_INO 0x30 /* uncorrectable error */ 309 #define SCZ_CE_INO 0x31 /* correctable ecc error */ 310 #define SCZ_PCIERR_A_INO 0x32 /* PCI A bus error */ 311 #define SCZ_PCIERR_B_INO 0x33 /* PCI B bus error */ 312 #define SCZ_SERR_INO 0x34 /* safari interface error */ 313 314 #define SCZ_JBUS_ESTAR_FULL (1UL << 0) /* full speed */ 315 #define SCZ_JBUS_ESTAR_HALF (1UL << 1) /* half speed */ 316 #define SCZ_JBUS_ESTAR_SLOW (1UL << 5) /* 1/32 speed */ 317 318 struct schizo_range { 319 u_int32_t cspace; 320 u_int32_t child_hi; 321 u_int32_t child_lo; 322 u_int32_t phys_hi; 323 u_int32_t phys_lo; 324 u_int32_t size_hi; 325 u_int32_t size_lo; 326 }; 327 328 #ifdef DEBUG 329 /* 330 * Register information from: 331 * Schizo Programmer's Reference Manual, September 30, 2007 332 * JIO JBUS to PCI Bridge ASIC, 20 July, 2007 333 * 334 * Some registers are write-only (WO), or can only be accessed when 335 * diagnostics mode is set up (Diag). 336 */ 337 struct schizo_regname { 338 const u_int64_t offset; 339 const int size; 340 const int n_reg; 341 #define REG_TYPE_SCHIZO 0x0001 342 #define REG_TYPE_TOMATILLO 0x0002 343 #define REG_TYPE_LEAF_A 0x0100 344 #define REG_TYPE_LEAF_B 0x0200 345 const int type; 346 const char * name; 347 }; 348 349 /* 0x01 */ 350 static const struct schizo_regname schizo_regnames[] = { 351 { 0x000000, 8, 0, 1, "UPA0 Address Match Register" }, 352 { 0x000000, 8, 0, 2, "UPA0 Offset Base Register" }, 353 { 0x000008, 8, 0, 1, "UPA0 Address Mask Register" }, 354 { 0x000008, 8, 0, 2, "UPA0 Offset Mask Register" }, 355 { 0x000010, 8, 0, 1, "UPA1 Address Match Register" }, 356 { 0x000010, 8, 0, 2, "UPA1 Offset Base Register" }, 357 { 0x000018, 8, 0, 1, "UPA1 Address Mask Register" }, 358 { 0x000018, 8, 0, 2, "UPA1 Offset Mask Register" }, 359 { 0x000020, 8, 0, 2, "NewLink Address Match Register" }, 360 { 0x000028, 8, 0, 2, "NewLink Address Mask Register" }, 361 { 0x000030, 8, 0, 2, "NewLinkAlt Address Match Register" }, 362 { 0x000038, 8, 0, 2, "NewLinkAlt Address Mask Register" }, 363 { 0x000040, 8, 0, 1, "PCI-A Mem Address Match Register" }, 364 { 0x000040, 8, 0, 2, "PCI-A Mem Offset Base Register" }, 365 { 0x000048, 8, 0, 1, "PCI-A Mem Address Mask Register" }, 366 { 0x000048, 8, 0, 2, "PCI-A Mem Offset Mask Register" }, 367 { 0x000050, 8, 0, 1, "PCI-A Cfg IO Address Match Register" }, 368 { 0x000050, 8, 0, 2, "PCI-A Cfg IO Offset Base Register" }, 369 { 0x000058, 8, 0, 1, "PCI-A Cfg IO Address Mask Register" }, 370 { 0x000058, 8, 0, 2, "PCI-A Cfg IO Offset Mask Register" }, 371 { 0x000060, 8, 0, 1, "PCI-B Mem Address Match Register" }, 372 { 0x000060, 8, 0, 2, "PCI-B Mem Offset Base Register" }, 373 { 0x000068, 8, 0, 1, "PCI-B Mem Address Mask Register" }, 374 { 0x000068, 8, 0, 2, "PCI-B Mem Offset Mask Register" }, 375 { 0x000070, 8, 0, 1, "PCI-B Cfg IO Address Match Register" }, 376 { 0x000070, 8, 0, 2, "PCI-B Cfg IO Offset Base Register" }, 377 { 0x000078, 8, 0, 1, "PCI-B Cfg IO Address Mask Register" }, 378 { 0x000078, 8, 0, 2, "PCI-B Cfg IO Offset Mask Register" }, 379 { 0x010000, 8, 0, 3, "Control/Status Register" }, 380 { 0x010008, 8, 0, 3, "Error Control Register" }, 381 { 0x010010, 8, 0, 3, "Interrupt Control Register" }, 382 { 0x010018, 8, 0, 3, "Error Log Register" }, 383 { 0x010020, 8, 0, 1, "ECC Control Register" }, 384 { 0x010020, 8, 0, 2, "Jbus Parity Control Register" }, 385 { 0x010030, 8, 0, 3, "UE AFSR" }, 386 { 0x010038, 8, 0, 3, "UE AFAR" }, 387 { 0x010040, 8, 0, 3, "CE AFSR" }, 388 { 0x010048, 8, 0, 3, "CE AFAR" }, 389 { 0x010050, 8, 0, 3, "Energy Star Control Register" }, 390 { 0x010058, 8, 0, 1, "Safari Soft Pause Register" }, 391 { 0x010058, 8, 0, 2, "Jbus Change Initiation Register" }, 392 { 0x011000, 8, 0, 3, "Queue Control Register" }, 393 { 0x012000, 8, 0x70, 3, "DTag Diagnostic Register" }, 394 { 0x013000, 8, 0x70, 3, "CTag Diagnostic Register" }, 395 { 0x014000, 8, 0x18, 3, "Safari Debug Register" }, 396 { 0x017000, 8, 0, 3, "Performance Control Register" }, 397 { 0x017008, 8, 0, 3, "Performance Counter Register" }, 398 { 0x017010, 8, 0, 2, "Reset_Gen Register" }, 399 { 0x017018, 8, 0, 2, "Reset_Source Register" }, 400 { 0x017020, 8, 0, 2, "UPA Reset Control Register" }, 401 { 0x060000, 1, 0, 2, "GPIO 0 Register" }, 402 { 0x060001, 1, 0, 2, "GPIO 1 Register" }, 403 { 0x062000, 1, 0, 2, "GPIO 2 Register" }, 404 { 0x062001, 1, 0, 2, "GPIO 3 Register" }, 405 { 0x064000, 8, 0, 2, "GPIO Data Register" }, 406 { 0x064008, 8, 0, 2, "GPIO Control Register" }, 407 { 0, 0, 0, 0, NULL } 408 }; 409 410 /* 0x02 */ 411 static const struct schizo_regname schizo_pbm_regnames[] = { 412 { 0x000100, 8, 0, 0x0102, "PCI Performance Monitor Control Register" }, 413 { 0x000108, 8, 0, 0x0102, "PCI Performance Counter Register" }, 414 { 0x000110, 8, 0, 0x0102, "PCI Idle Check Diagnostics Register" }, 415 { 0x002000, 8, 0, 0x0303, "PCI Control/Status Register" }, 416 { 0x002010, 8, 0, 0x0303, "PCI AFSR" }, 417 { 0x002018, 8, 0, 0x0303, "PCI AFAR" }, 418 { 0x002020, 8, 0, 0x0303, "PCI Diagnostic Register" }, 419 { 0x002028, 8, 0, 0x0303, "PCI Energy Star Register" }, 420 { 0x002030, 8, 0, 0x0302, "PCI Target Retry Limit" }, 421 { 0x002038, 8, 0, 0x0302, "PCI Target Latency Timer" }, 422 /* See tomatillo_scratch_regnames[] */ 423 { 0x002240, 8, 0, 0x0102, "Interrupt Routing Register" }, 424 { 0x002490, 8, 0, 0x0302, "PCI Target Address Space Register" }, 425 { 0x002498, 8, 0, 0x0302, "PCI Target Error VA Log Register" }, 426 { 0, 0, 0, 0, NULL } 427 }; 428 429 /* 0x04 */ 430 static const struct schizo_regname tomatillo_scratch_regnames[] = { 431 { 0x002040, 8, 0x1f8, 2, "Scratch Pad Register" }, 432 { 0, 0, 0, 0, NULL } 433 }; 434 435 /* 0x08 */ 436 static const struct schizo_regname schizo_iommu_regnames[] = { 437 { 0x000200, 8, 0, 3, "IOMMU Control Register" }, 438 { 0x000208, 8, 0, 3, "TSB Base Address Reg" }, 439 /* WO { 0x000210, 8, 0, 3, "IOMMU Flush Page Register" }, */ 440 /* WO { 0x000218, 8, 0, 3, "IOMMU Flush Context Register" }, */ 441 { 0x000220, 8, 0, 2, "Translation Fault Address Register" }, 442 { 0x00a400, 8, 0, 1, "TLB Compare Setup Diag Reg" }, 443 { 0x00a408, 8, 0, 1, "TLB Compare Result Diag Reg" }, 444 /* Diag { 0x00a500, 8, 0x7f, 1, "IOMMU LRU Queue Diag Reg" }, */ 445 /* Diag { 0x00a580, 8, 0x7f, 1, "TLB Tag Diag Reg" }, */ 446 /* Diag { 0x00a600, 8, 0x7f, 1, "TLB Data RAM Diag Reg" }, */ 447 { 0, 0, 0, 0, NULL } 448 }; 449 450 /* 0x10 */ 451 static const struct schizo_regname schizo_stream_regnames[] = { 452 { 0x002800, 8, 0, 1, "Streaming Cache Control Reg" }, 453 /* WO { 0x002808, 8, 0, 1, "Streaming Cache Page Flush/Invalidate Reg" }, */ 454 /* WO { 0x002810, 8, 0, 1, "Streaming Cache Flush Synchronization Reg" }, */ 455 /* WO { 0x002818, 8, 0, 1, "Streaming Cache Context Flush/Invalidate Reg" }, */ 456 { 0x00b000, 8, 0x7ff, 1, "Streaming Cache Data RAM Diagnostic" }, 457 /* Diag { 0x00b800, 8, 0x7ff, 1, "Streaming Cache Error Status Diagnostic" }, */ 458 { 0x00ba00, 8, 0x7f, 1, "Streaming Cache Page Tag Diagnostic" }, 459 { 0x00bb00, 8, 0x7f, 1, "Streaming Cache Line Tag Diagnostic" }, 460 { 0x010000, 8, 0x7fff, 1, "Streaming Cache Context Match Reg" }, 461 { 0, 0, 0, 0, NULL } 462 }; 463 464 /* 0x20 */ 465 static const struct schizo_regname schizo_intr_regnames[] = { 466 { 0x001000, 8, 0x1ff, 3, "Interrupt Mapping Register for interrupt INO" }, 467 { 0x001400, 8, 0x1ff, 3, "Clear Interrupt Register for interrupt INO" }, 468 { 0x001a00, 8, 0, 3, "Interrupt Retry Register" }, 469 { 0x001a08, 8, 0, 3, "PCI Consistent DMA Flush/Sync Register" }, 470 { 0x006000, 8, 0, 3, "UPA Port 0 Interrupt Mapping Register" }, 471 { 0x008000, 8, 0, 3, "UPA Port 1 Interrupt Mapping Register" }, 472 { 0x00a800, 8, 0, 3, "PCI Int State Diag Register" }, 473 { 0x00a808, 8, 0, 3, "OBIO and Internal Int State Diag Register" }, 474 { 0, 0, 0, 0, NULL } 475 }; 476 477 /* 0x40 */ 478 static const struct schizo_regname tomatillo_ichip_regnames[] = { 479 { 0x001000, 8, 0x1ff, 3, "Interrupt Mapping Register for interrupt INO" }, 480 { 0x001400, 8, 0x1ff, 3, "Clear Interrupt Register for interrupt INO" }, 481 { 0x001a00, 8, 0, 3, "Interrupt Retry Register" }, 482 { 0x001a10, 8, 0, 3, "I-chip DMA Flush/Sync Complete Register" }, 483 { 0x001a18, 8, 0, 3, "I-chip DMA Flush/Sync Pending Register" }, 484 { 0x006000, 8, 0, 3, "UPA Port 0 Interrupt Mapping Register" }, 485 { 0x008000, 8, 0, 3, "UPA Port 1 Interrupt Mapping Register" }, 486 { 0x00a800, 8, 0, 3, "PCI Int State Diag Register" }, 487 { 0x00a808, 8, 0, 3, "OBIO and Internal Int State Diag Register" }, 488 { 0, 0, 0, 0, NULL } 489 }; 490 #endif 491