1 /* $NetBSD: rge.c,v 1.8 2021/03/25 03:44:25 rin Exp $ */
2
3 /*-
4 * Copyright (c) 2007 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Tohru Nishimura.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/param.h>
33
34 #include <netinet/in.h>
35 #include <netinet/in_systm.h>
36
37 #include <lib/libsa/stand.h>
38 #include <lib/libsa/net.h>
39
40 #include "globals.h"
41
42 /*
43 * - reverse endian access every CSR.
44 * - no vtophys() translation, vaddr_t == paddr_t.
45 * - PIPT writeback cache aware.
46 */
47 #define CSR_WRITE_1(l, r, v) out8((l)->csr+(r), (v))
48 #define CSR_READ_1(l, r) in8((l)->csr+(r))
49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
50 #define CSR_READ_2(l, r) in16rb((l)->csr+(r))
51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
52 #define CSR_READ_4(l, r) in32rb((l)->csr+(r))
53 #define VTOPHYS(va) (uint32_t)(va)
54 #define DEVTOV(pa) (uint32_t)(pa)
55 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz))
56 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz))
57 #define DELAY(n) delay(n)
58 #define ALLOC(T,A) (T *)allocaligned(sizeof(T),(A))
59
60 struct desc {
61 uint32_t xd0, xd1, xd2, xd3;
62 };
63 #define T0_OWN 0x80000000 /* loaded for HW to send */
64 #define T0_EOR 0x40000000 /* end of ring */
65 #define T0_FS 0x20000000 /* first descriptor */
66 #define T0_LS 0x10000000 /* last descriptor */
67 #define T0_FRMASK 0x0000ffff
68
69 #define R0_OWN 0x80000000 /* empty for HW to load anew */
70 #define R0_EOR 0x40000000 /* end mark to form a ring */
71 #define R0_BUFLEN 0x00003ff8 /* max frag. size to receive */
72 #define R0_FS 0x20000000 /* start of frame */
73 #define R0_LS 0x10000000 /* end of frame */
74 #define R0_RES 0x00200000 /* Rx error summary */
75 #define R0_RUNT 0x00100000 /* runt frame received */
76 #define R0_CRC 0x00080000 /* CRC error found */
77 #define R0_FRMASK 0x00003fff /* 13:0 frame length */
78
79 #define RGE_IDR0 0x00 /* MAC address [0] */
80 #define RGE_IDR1 0x01 /* MAC address [1] */
81 #define RGE_IDR2 0x02 /* MAC address [2] */
82 #define RGE_IDR3 0x03 /* MAC address [3] */
83 #define RGE_IDR4 0x04 /* MAC address [4] */
84 #define RGE_IDR5 0x05 /* MAC address [5] */
85 #define RGE_TNPDS 0x20 /* Tx descriptor base paddr */
86 #define RGE_THPDS 0x28 /* high pro. Tx des. base paddr */
87 #define RGE_CR 0x37 /* command */
88 #define CR_RESET (1U << 4) /* reset S1C */
89 #define CR_RXEN (1U << 3) /* Rx enable */
90 #define CR_TXEN (1U << 2) /* Tx enable */
91 #define RGE_TPPOLL 0x38 /* activate desc polling */
92 #define RGE_IMR 0x3c /* interrupt mask */
93 #define RGE_ISR 0x3e /* interrupt status */
94 #define RGE_TCR 0x40 /* Tx control */
95 #define TCR_MAXDMA 0x0700 /* 10:8 Tx DMA burst size */
96 #define RGE_RCR 0x44 /* Rx control */
97 #define RCR_RXTFH 0xe000 /* 15:13 Rx FIFO threshold */
98 #define RCR_MAXDMA 0x0700 /* 10:8 Rx DMA burst size */
99 #define RCR_AE (1U << 5) /* accept error frame */
100 #define RCR_RE (1U << 4) /* accept runt frame */
101 #define RCR_AB (1U << 3) /* accept broadcast frame */
102 #define RCR_AM (1U << 2) /* accept multicast frame */
103 #define RCR_APM (1U << 1) /* accept unicast frame */
104 #define RCR_AAP (1U << 0) /* promiscuous */
105 #define RGE_EECMD 0x50 /* EEPROM command register */
106 #define EECMD_LOCK 0x00
107 #define EECMD_UNLOCK 0xc0
108 #define RGE_PHYAR 0x60 /* PHY access */
109 #define RGE_PHYSR 0x6c /* PHY status */
110 #define RGE_RMS 0xda /* Rx maximum frame size */
111 #define RGE_RDSAR 0xe4 /* Rx descriptor base paddr */
112 #define RGE_ETTHR 0xec /* Tx threshold */
113
114 #define FRAMESIZE 1536
115
116 struct local {
117 struct desc txd[2]; /* 256B align */
118 uint8_t _hole0[256 - 2 * sizeof(struct desc)];
119 struct desc rxd[2]; /* 256B align */
120 uint8_t _hole1[256 - 2 * sizeof(struct desc)];
121 uint8_t rxstore[2][FRAMESIZE];
122 unsigned csr, tx, rx;
123 unsigned phy, bmsr, anlpar;
124 unsigned tcr, rcr;
125 };
126
127 static int mii_read(struct local *, int, int);
128 static void mii_write(struct local *, int, int, int);
129 static void mii_initphy(struct local *);
130 static void mii_dealan(struct local *, unsigned);
131
132 int
rge_match(unsigned tag,void * data)133 rge_match(unsigned tag, void *data)
134 {
135 unsigned v;
136
137 v = pcicfgread(tag, PCI_ID_REG);
138 switch (v) {
139 case PCI_DEVICE(0x10ec, 0x8167):
140 case PCI_DEVICE(0x10ec, 0x8169):
141 return 1;
142 }
143 return 0;
144 }
145
146 void *
rge_init(unsigned tag,void * data)147 rge_init(unsigned tag, void *data)
148 {
149 unsigned val;
150 struct local *l;
151 struct desc *txd, *rxd;
152 uint32_t reg;
153 uint8_t *en;
154
155 l = ALLOC(struct local, 256); /* desc alignment */
156 memset(l, 0, sizeof(struct local));
157 l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* use mem space */
158
159 CSR_WRITE_1(l, RGE_CR, CR_RESET);
160 do {
161 val = CSR_READ_1(l, RGE_CR);
162 } while (val & CR_RESET);
163
164 mii_initphy(l);
165 en = data;
166
167 if (brdtype == BRD_QNAPTS) {
168 /* read the MAC from flash and write it into the ID-Regs */
169 read_mac_from_flash(en);
170
171 CSR_WRITE_1(l, RGE_EECMD, EECMD_UNLOCK);
172 reg = en[0] | (en[1] << 8) | (en[2] << 16) | (en[3] << 24);
173 CSR_WRITE_4(l, RGE_IDR0, reg);
174 reg = en[4] | (en[5] << 8);
175 CSR_WRITE_4(l, RGE_IDR4, reg);
176 CSR_WRITE_1(l, RGE_EECMD, EECMD_LOCK);
177 } else {
178 /* pretent the ID-Regs have the correct address */
179 en[0] = CSR_READ_1(l, RGE_IDR0);
180 en[1] = CSR_READ_1(l, RGE_IDR1);
181 en[2] = CSR_READ_1(l, RGE_IDR2);
182 en[3] = CSR_READ_1(l, RGE_IDR3);
183 en[4] = CSR_READ_1(l, RGE_IDR4);
184 en[5] = CSR_READ_1(l, RGE_IDR5);
185 }
186
187 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
188 en[0], en[1], en[2], en[3], en[4], en[5]);
189 DPRINTF(("PHY %d (%04x.%04x)\n", l->phy,
190 mii_read(l, l->phy, 2), mii_read(l, l->phy, 3)));
191
192 mii_dealan(l, 5);
193
194 /* speed and duplexity can be seen in PHYSR */
195 val = CSR_READ_1(l, RGE_PHYSR);
196 if (val & (1U << 4))
197 printf("1000Mbps");
198 if (val & (1U << 3))
199 printf("100Mbps");
200 if (val & (1U << 2))
201 printf("10Mbps");
202 if (val & (1U << 0))
203 printf("-FDX");
204 printf("\n");
205
206 txd = &l->txd[0];
207 txd[1].xd0 = htole32(T0_EOR);
208 rxd = &l->rxd[0];
209 rxd[0].xd0 = htole32(R0_OWN | FRAMESIZE);
210 rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
211 rxd[1].xd0 = htole32(R0_OWN | R0_EOR | FRAMESIZE);
212 rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
213 wbinv(l, sizeof(struct local));
214 l->tx = l->rx = 0;
215
216 l->tcr = (03 << 24) | (07 << 8);
217 l->rcr = (07 << 13) | (07 << 8) | RCR_APM;
218 CSR_WRITE_1(l, RGE_CR, CR_TXEN | CR_RXEN);
219 CSR_WRITE_1(l, RGE_ETTHR, 0x3f);
220 CSR_WRITE_2(l, RGE_RMS, FRAMESIZE);
221 CSR_WRITE_4(l, RGE_TCR, l->tcr);
222 CSR_WRITE_4(l, RGE_RCR, l->rcr);
223 CSR_WRITE_4(l, RGE_TNPDS, VTOPHYS(txd));
224 CSR_WRITE_4(l, RGE_RDSAR, VTOPHYS(rxd));
225 CSR_WRITE_4(l, RGE_TNPDS + 4, 0);
226 CSR_WRITE_4(l, RGE_RDSAR + 4, 0);
227 CSR_WRITE_2(l, RGE_ISR, ~0);
228 CSR_WRITE_2(l, RGE_IMR, 0);
229 return l;
230 }
231
232 int
rge_send(void * dev,char * buf,unsigned len)233 rge_send(void *dev, char *buf, unsigned len)
234 {
235 struct local *l = dev;
236 volatile struct desc *txd;
237 unsigned loop, ret;
238 char tmp[60];
239
240 ret = len;
241 /* RTL does not stretch <60 Tx frame */
242 if (len < 60) {
243 memcpy(tmp, buf, len);
244 buf = tmp;
245 memset(buf + len, 0, 60 - len);
246 len = 60;
247 }
248 wbinv(buf, len);
249 txd = &l->txd[l->tx];
250 txd->xd2 = htole32(VTOPHYS(buf));
251 txd->xd0 &= htole32(T0_EOR);
252 txd->xd0 |= htole32(T0_OWN | T0_FS | T0_LS | (len & T0_FRMASK));
253 wbinv(txd, sizeof(struct desc));
254 CSR_WRITE_1(l, RGE_TPPOLL, 0x40);
255 loop = 100;
256 do {
257 if ((le32toh(txd->xd0) & T0_OWN) == 0)
258 goto done;
259 DELAY(10);
260 inv(txd, sizeof(struct desc));
261 } while (--loop > 0);
262 printf("xmit failed\n");
263 return -1;
264 done:
265 l->tx ^= 1;
266 return ret;
267 }
268
269 int
rge_recv(void * dev,char * buf,unsigned maxlen,unsigned timo)270 rge_recv(void *dev, char *buf, unsigned maxlen, unsigned timo)
271 {
272 struct local *l = dev;
273 volatile struct desc *rxd;
274 unsigned bound, rxstat, len;
275 uint8_t *ptr;
276
277 bound = 1000 * timo;
278 #if 0
279 printf("recving with %u sec. timeout\n", timo);
280 #endif
281 again:
282 rxd = &l->rxd[l->rx];
283 do {
284 inv(rxd, sizeof(struct desc));
285 rxstat = le32toh(rxd->xd0);
286 if ((rxstat & R0_OWN) == 0)
287 goto gotone;
288 DELAY(1000); /* 1 milli second */
289 } while (--bound > 0);
290 errno = 0;
291 return -1;
292 gotone:
293 if (rxstat & R0_RES) {
294 rxd->xd0 &= htole32(R0_EOR);
295 rxd->xd0 |= htole32(R0_OWN | FRAMESIZE);
296 wbinv(rxd, sizeof(struct desc));
297 l->rx ^= 1;
298 goto again;
299 }
300 len = rxstat & R0_FRMASK;
301 if (len > maxlen)
302 len = maxlen;
303 ptr = l->rxstore[l->rx];
304 inv(ptr, len);
305 memcpy(buf, ptr, len);
306 rxd->xd0 &= htole32(R0_EOR);
307 rxd->xd0 |= htole32(R0_OWN | FRAMESIZE);
308 wbinv(rxd, sizeof(struct desc));
309 l->rx ^= 1;
310 return len;
311 }
312
313 static int
mii_read(struct local * l,int phy,int reg)314 mii_read(struct local *l, int phy, int reg)
315 {
316 unsigned v;
317
318 v = reg << 16;
319 CSR_WRITE_4(l, RGE_PHYAR, v);
320 DELAY(1000);
321 do {
322 DELAY(100);
323 v = CSR_READ_4(l, RGE_PHYAR);
324 } while ((v & (1U << 31)) == 0); /* wait for 0 -> 1 */
325 return v & 0xffff;
326 }
327
328 static void
mii_write(struct local * l,int phy,int reg,int data)329 mii_write(struct local *l, int phy, int reg, int data)
330 {
331 unsigned v;
332
333 v = (reg << 16) | (data & 0xffff) | (1U << 31);
334 CSR_WRITE_4(l, RGE_PHYAR, v);
335 DELAY(1000);
336 do {
337 DELAY(100);
338 v = CSR_READ_4(l, RGE_PHYAR);
339 } while (v & (1U << 31)); /* wait for 1 -> 0 */
340 }
341
342 #define MII_BMCR 0x00 /* Basic mode control register (rw) */
343 #define BMCR_RESET 0x8000 /* reset */
344 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */
345 #define BMCR_ISO 0x0400 /* isolate */
346 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */
347 #define MII_BMSR 0x01 /* Basic mode status register (ro) */
348 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */
349 #define BMSR_LINK 0x0004 /* Link status */
350 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */
351 #define ANAR_FC 0x0400 /* local device supports PAUSE */
352 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
353 #define ANAR_TX 0x0080 /* local device supports 100bTx */
354 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */
355 #define ANAR_10 0x0020 /* local device supports 10bT */
356 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */
357 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
358 #define MII_GTCR 0x09 /* 1000baseT control */
359 #define GANA_1000TFDX 0x0200 /* advertise 1000baseT FDX */
360 #define GANA_1000THDX 0x0100 /* advertise 1000baseT HDX */
361 #define MII_GTSR 0x0a /* 1000baseT status */
362 #define GLPA_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */
363 #define GLPA_1000THDX 0x0400 /* link partner 1000baseT HDX capable */
364 #define GLPA_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */
365
366 static void
mii_initphy(struct local * l)367 mii_initphy(struct local *l)
368 {
369 int bound, ctl, phy, sts;
370
371 phy = 7; /* internal rgephy, always at 7 */
372 ctl = mii_read(l, phy, MII_BMCR);
373 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET);
374 bound = 100;
375 do {
376 DELAY(10);
377 ctl = mii_read(l, phy, MII_BMCR);
378 if (ctl == 0xffff) {
379 printf("MII: PHY %d has died after reset\n", phy);
380 return;
381 }
382 } while (bound-- > 0 && (ctl & BMCR_RESET));
383 if (bound == 0) {
384 printf("PHY %d reset failed\n", phy);
385 }
386 ctl &= ~BMCR_ISO;
387 mii_write(l, phy, MII_BMCR, ctl);
388 sts = mii_read(l, phy, MII_BMSR) |
389 mii_read(l, phy, MII_BMSR); /* read twice */
390 l->phy = phy;
391 l->bmsr = sts;
392 }
393
394 void
mii_dealan(struct local * l,unsigned timo)395 mii_dealan(struct local *l, unsigned timo)
396 {
397 unsigned anar, gtcr, bound;
398
399 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA;
400 anar |= ANAR_FC;
401 gtcr = GANA_1000TFDX | GANA_1000THDX;
402 mii_write(l, l->phy, MII_ANAR, anar);
403 mii_write(l, l->phy, MII_GTCR, gtcr);
404 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
405 l->anlpar = 0;
406 bound = getsecs() + timo;
407 do {
408 l->bmsr = mii_read(l, l->phy, MII_BMSR) |
409 mii_read(l, l->phy, MII_BMSR); /* read twice */
410 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) {
411 l->anlpar = mii_read(l, l->phy, MII_ANLPAR);
412 break;
413 }
414 DELAY(10 * 1000);
415 } while (getsecs() < bound);
416 return;
417 }
418