1 /*        $NetBSD: vrc4172reg.h,v 1.6 2022/04/08 10:17:53 andvar Exp $          */
2 
3 /*
4  * Copyright (c) 2000 SATO Kazumi.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions, and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 /*
29  * Vrc4172 (Vr4121 companion chip) device units definitions
30  */
31 
32 #define VRC2_GPIOL_ADDR       0x15001080          /* GPIO (0..15) */
33 #define VRC2_PCS_ADDR         0x15001090          /* PCS Programmable chip selects */
34 #define VRC2_GPIOH_ADDR       0x150010c0          /* GPIO (16..23) */
35 #define VRC2_PMU_ADDR         0x15003800          /* PMU */
36 #define VRC2_ICU_ADDR         0x15003808          /* ICU */
37 #define VRC2_COM_ADDR         0x15003810          /* NS16550A compat */
38 #define VRC2_PIO_ADDR         0x15003820          /* IEEE1284 parallel */
39 #define VRC2_PS2_ADDR         0x15003870          /* PS/2 controller */
40 #define VRC2_PWM_ADDR         0x15003880          /* PWM (backlight pulus) controller */
41 
42 /* end */
43