1 #ifndef INTERWAVEREG_H 2 #define INTERWAVEREG_H 3 4 /* $NetBSD: interwavereg.h,v 1.10 2024/02/09 22:08:34 andvar Exp $ */ 5 6 /* 7 * Copyright (c) 1997 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Kari Mettinen 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 #define IW_LINELEVEL_MAX ((1L << 10) - 1) 36 #define IW_LINELEVEL_CODEC_MAX ((1L << 10) - 1) 37 38 #define IW_OUTPUT_CLASS 10 39 #define IW_INPUT_CLASS 11 40 #define IW_RECORD_CLASS 12 41 42 43 #define IW_MIC_IN 11 44 #define IW_MIC_IN_LVL 0 45 46 /* these 2 are hw dependent values */ 47 #define IW_RIGHT_MIC_IN_PORT 0x16 48 #define IW_LEFT_MIC_IN_PORT 0x17 49 50 #define IW_AUX1 12 51 #define IW_AUX1_LVL 1 52 53 #define IW_RIGHT_AUX1_PORT 0x02 54 #define IW_LEFT_AUX1_PORT 0x03 55 56 #define IW_AUX2 13 57 #define IW_AUX2_LVL 2 58 59 #define IW_RIGHT_AUX2_PORT 0x04 60 #define IW_LEFT_AUX2_PORT 0x05 61 62 #define IW_LINE_IN 14 63 #define IW_LINE_IN_LVL 3 64 65 #define IW_RIGHT_LINE_IN_PORT 0x12 66 #define IW_LEFT_LINE_IN_PORT 0x13 67 68 #define IW_LINE_OUT 15 69 #define IW_LINE_OUT_LVL 4 70 71 #define IW_RIGHT_LINE_OUT_PORT 0x19 72 #define IW_LEFT_LINE_OUT_PORT 0x1b 73 74 #define IW_RECORD_SOURCE 5 75 76 #define IW_REC 16 77 #define IW_REC_LVL 6 78 #define IW_REC_LEFT_PORT 0x00 79 #define IW_REC_RIGHT_PORT 0x01 80 81 #define IW_DAC 18 82 #define IW_DAC_LVL 7 83 #define IW_LEFT_DAC_PORT 0x06 84 #define IW_RIGHT_DAC_PORT 0x07 85 86 #define IW_LOOPBACK 19 87 #define IW_LOOPBACK_LVL 8 88 #define IW_LOOPBACK_PORT 0x0d 89 90 #define IW_MONO_IN 20 91 #define IW_MONO_IN_LVL 9 92 #define IW_MONO_IN_PORT 0x1a 93 94 #define IW_LINE_IN_SRC 0 95 #define IW_AUX1_SRC 1 96 #define IW_MIC_IN_SRC 2 97 #define IW_MIX_OUT_SRC 3 98 99 100 /* DMA flags */ 101 102 #define IW_PLAYBACK 1L 103 #define IW_RECORD 2L 104 105 #define ADDR_HIGH(a) (u_short)((a) >> 7) 106 #define ADDR_LOW(a) (u_short)((a) << 9) 107 108 #define MIDI_TX_IRQ 0x01 109 #define MIDI_RX_IRQ 0x02 110 #define ALIB_TIMER1_IRQ 0x04 111 #define ALIB_TIMER2_IRQ 0x08 112 #define UASBCI 0x45 /* UASBCI index */ 113 #define SAMPLE_CONTROL 0x49 /* Not used by IW */ 114 #define SET_VOICES 0x0E 115 #define SAVI_WR 0x0E 116 #define WAVETABLE_IRQ 0x20 117 #define ENVELOPE_IRQ 0x40 118 #define DMA_TC_IRQ 0x80 119 120 #define GEN_INDEX 0x03 /* IGIDX offset into p3xr */ 121 #define VOICE_SELECT 0x02 /* SVSR offset into p3xr */ 122 #define VOICE_IRQS 0x8F /* SVII index (read) */ 123 #define URSTI 0x4C /* URSTI index */ 124 #define GF1_SET 0x01 /* URSTI[0] */ 125 #define GF1_OUT_ENABLE 0x02 /* URSTI[1] */ 126 #define GF1_IRQ_ENABLE 0x04 /* URSTI[2] */ 127 #define GF1_RESET 0xFE /* URSTI[0]=0 */ 128 #define VOICE_VOLUME_IRQ 0x04 /* SVII[2] */ 129 #define VOICE_WAVE_IRQ 0x08 /* SVII[3] */ 130 #define VC_IRQ_ENABLE 0x20 /* SACI[5] or SVCI[5]*/ 131 #define VOICE_NUMBER 0x1F /* Mask for SVII[4:0] */ 132 #define VC_IRQ_PENDING 0x80 /* SACI[7] or SVCI[7] */ 133 #define VC_DIRECT 0x40 /* SACI[6] or SVCI[6]*/ 134 #define VC_DATA_WIDTH 0x04 /* SACI[2] */ 135 #define VOICE_STOP 0x02 /* SACI[1] */ 136 #define VOICE_STOPPED 0x01 /* SACI[0] */ 137 #define VOLUME_STOP 0x02 /* SVCI[1] */ 138 #define VOLUME_STOPPED 0x01 /* SVCI[0] */ 139 #define VC_ROLLOVER 0x04 /* SVCI[2] */ 140 #define VC_LOOP_ENABLE 0x08 /* SVCI[3] or SACI[3]*/ 141 #define VC_BI_LOOP 0x10 /* SVCI[4] or SACI[4]*/ 142 #define VOICE_OFFSET 0x20 /* SMSI[5] */ 143 #define VOLUME_RATE0 0x00 /* SVRI[7:6]=(0,0) */ 144 #define VOLUME_RATE1 0x40 /* SVRI[7:6]=(0,1) */ 145 #define VOLUME_RATE2 0x80 /* SVRI[7:6]=(1,0) */ 146 #define VOLUME_RATE3 0xC0 /* SVRI[7:6]=(1,1) */ 147 148 #define CSR1R 0x02 149 #define CPDR 0x03 150 #define CRDR 0x03 151 152 #define SHUT_DOWN 0x7E /* shuts InterWave down */ 153 #define POWER_UP 0xFE /* enables all modules */ 154 #define CODEC_PWR_UP 0x81 /* enables Codec Analog Ckts */ 155 #define CODEC_PWR_DOWN 0x01 /* disables Codec Analog Ckts */ 156 #define CODEC_REC_UP 0x82 /* Enables Record Path */ 157 #define CODEC_REC_DOWN 0x02 /* Disables Record Path */ 158 #define CODEC_PLAY_UP 0x84 /* Enables Playback Path */ 159 #define CODEC_PLAY_DOWN 0x04 /* Disables Playback Path */ 160 #define CODEC_IRQ_ENABLE 0x02 /* CEXTI[2] */ 161 #define CODEC_TIMER_IRQ 0x40 /* CSR3I[6] */ 162 #define CODEC_REC_IRQ 0x20 /* CSR3I[5] */ 163 #define CODEC_PLAY_IRQ 0x10 /* CSR3I[4] */ 164 #define CODEC_INT 0x01 /* CSR1R[0] */ 165 #define MONO_INPUT 0x80 /* CMONOI[7] */ 166 #define MONO_OUTPUT 0x40 /* CMONOI[6] */ 167 #define MIDI_UP 0x88 /* Enables MIDI ports */ 168 #define MIDI_DOWN 0x08 /* Disables MIDI ports */ 169 #define SYNTH_UP 0x90 /* Enables Synthesizer */ 170 #define SYNTH_DOWN 0x10 /* Disables Synthesizer */ 171 #define LMC_UP 0xA0 /* Enables LM Module */ 172 #define LMC_DOWN 0x20 /* Disables LM Module */ 173 #define XTAL24_UP 0xC0 /* Enables 24MHz Osc */ 174 #define XTAL24_DOWN 0x40 /* Disables 24MHz Osc */ 175 #define PPWRI 0xF2 /* PPWRI index */ 176 #define PLAY 0x0F 177 #define REC 0x1F 178 #define LEFT_AUX1_INPUT 0x02 179 #define RIGHT_AUX1_INPUT 0x03 180 #define LEFT_AUX2_INPUT 0x04 181 #define RIGHT_AUX2_INPUT 0x05 182 #define LEFT_LINE_IN 0x12 183 #define RIGHT_LINE_IN 0x13 184 #define LEFT_LINE_OUT 0x19 185 #define RIGHT_LINE_OUT 0x1B 186 #define LEFT_SOURCE 0x00 187 #define RIGHT_SOURCE 0x01 188 #define LINE_IN 0x00 189 #define AUX1_IN 0x40 190 #define MIC_IN 0x80 191 #define MIX_IN 0xC0 192 #define LEFT_DAC 0x06 193 #define RIGHT_DAC 0x07 194 #define LEFT_MIC_IN 0x16 195 #define RIGHT_MIC_IN 0x17 196 #define CUPCTI 0x0E 197 #define CLPCTI 0x0F 198 #define CURCTI 0x1E 199 #define CLRCTI 0x1F 200 #define CLAX1I 0x02 201 #define CRAX1I 0x03 202 #define CLAX2I 0x04 203 #define CRAX2I 0x05 204 #define CLLICI 0x12 205 #define CRLICI 0x13 206 #define CLOAI 0x19 207 #define CROAI 0x1B 208 #define CLICI 0x00 209 #define CRICI 0x01 210 #define CLDACI 0x06 211 #define CRDACI 0x07 212 #define CPVFI 0x1D 213 214 #define MAX_DMA 0x07 215 #define DMA_DECREMENT 0x20 216 #define AUTO_INIT 0x10 217 #define DMA_READ 0x01 218 #define DMA_WRITE 0x02 219 #define AUTO_READ 0x03 220 #define AUTO_WRITE 0x04 221 #define IDMA_INV 0x0400 222 #define IDMA_WIDTH_16 0x0100 223 224 #define LDMACI 0x41 /* Index */ 225 #define DMA_INV 0x80 226 #define DMA_IRQ_ENABLE 0x20 227 #define DMA_IRQ_PENDING 0x40 /* on reads of LDMACI[6] */ 228 #define DMA_DATA_16 0x40 /* on writes to LDMACI[6] */ 229 #define DMA_WIDTH_16 0x04 /* 1=16-bit, 0=8-bit (DMA channel) */ 230 #define DMA_RATE 0x18 /* 00=fastest,...,11=slowest */ 231 #define DMA_UPLOAD 0x02 /* From LM to PC */ 232 #define DMA_ENABLE 0x01 233 234 #define GUS_MODE 0x00 /* SGMI[0]=0 */ 235 #define ENH_MODE 0x01 /* SGMI[0]=1 */ 236 #define ENABLE_LFOS 0x02 /* SGMI[1] */ 237 #define NO_WAVETABLE 0x04 /* SGMI[2] */ 238 #define RAM_TEST 0x08 /* SGMI[3] */ 239 240 #define DMA_SET_MASK 0x04 241 242 #define VOICE_STOP 0x02 /* SACI[1] */ 243 #define VOICE_STOPPED 0x01 /* SACI[0] */ 244 245 #define LDSALI 0x42 246 #define LDSAHI 0x50 247 #define LMALI 0x43 248 #define LMAHI 0x44 249 #define LMCFI 0x52 250 #define LMCI 0x53 251 #define LMFSI 0x56 252 #define LDIBI 0x58 253 #define LDICI 0x57 254 #define LMSBAI 0x51 255 #define LMRFAI 0x54 256 #define LMPFAI 0x55 257 #define SVCI_RD 0x8D 258 #define SVCI_WR 0x0D 259 #define SACI_RD 0x80 260 #define SACI_WR 0x00 261 #define SALI_RD 0x8B 262 #define SALI_WR 0x0B 263 #define SAHI_RD 0x8A 264 #define SAHI_WR 0x0A 265 #define SASHI_RD 0x82 266 #define SASHI_WR 0x02 267 #define SASLI_RD 0x83 268 #define SASLI_WR 0x03 269 #define SAEHI_RD 0x84 270 #define SAEHI_WR 0x04 271 #define SAELI_RD 0x85 272 #define SAELI_WR 0x05 273 #define SVRI_RD 0x86 274 #define SVRI_WR 0x06 275 #define SVSI_RD 0x87 276 #define SVSI_WR 0x07 277 #define SVEI_RD 0x88 278 #define SVEI_WR 0x08 279 #define SVLI_RD 0x89 280 #define SVLI_WR 0x09 281 #define SROI_RD 0x8C 282 #define SROI_WR 0x0C 283 #define SLOI_RD 0x93 284 #define SLOI_WR 0x13 285 #define SMSI_RD 0x95 286 #define SMSI_WR 0x15 287 #define SGMI_RD 0x99 288 #define SGMI_WR 0x19 289 #define SFCI_RD 0x81 290 #define SFCI_WR 0x01 291 #define SUAI_RD 0x90 292 #define SUAI_WR 0x10 293 #define SVII 0x8F 294 #define CMODEI 0x0C /* index for CMODEI */ 295 #define CMONOI 0x1A 296 #define CFIG3I 0x11 297 #define CFIG2I 0x10 298 #define CLTIMI 0x14 299 #define CUTIMI 0x15 300 #define CSR3I 0x18 /* Index to CSR3I (Interrupt Status) */ 301 #define CEXTI 0x0A /* Index to External Control Register */ 302 #define CFIG1I 0x09 /* Index to Codec Conf Reg 1 */ 303 #define CSR2I 0x0B /* Index to Codec Stat Reg 2 */ 304 #define CPDFI 0x08 /* Index to Play Data Format Reg */ 305 #define CRDFI 0x1C /* Index to Rec Data Format Reg */ 306 #define CLMICI 0x16 /* Index to Left Mic Input Ctrl Register */ 307 #define CRMICI 0x17 /* Index to Right Mic Input Ctrl Register */ 308 #define CLCI 0x0D /* Index to Loopback Ctrl Register */ 309 #define IVERI 0x5B /* Index to register IVERI */ 310 #define IDECI 0x5A 311 #define ICMPTI 0x59 312 #define CODEC_MODE1 0x00 313 #define CODEC_MODE2 0x40 314 #define CODEC_MODE3 0x6C /* Enhanced Mode */ 315 #define CODEC_STATUS1 0x01 316 #define CODEC_STATUS2 0x0B /* Index to CSR2I */ 317 #define CODEC_STATUS3 0x18 /* Index to CSR3I */ 318 #define PLAYBACK 0x01 /* Enable playback path CFIG1I[0]=1*/ 319 #define RECORD 0x02 /* Enable Record path CFIG1I[1]=1*/ 320 #define TIMER_ENABLE 0x40 /* CFIG2I[6] */ 321 #define CODEC_MCE 0x40 /* CIDXR[6] */ 322 #define CALIB_IN_PROGRESS 0x20 /* CSR2I[5] */ 323 #define CODEC_INIT 0x80 /* CIDXR[7] */ 324 #define BIT16_BIG 0xC0 /* 16-bit signed, big endian */ 325 #define IMA_ADPCM 0xA0 /* IMA-compliant ADPCM */ 326 #define BIT8_ALAW 0x60 /* 8-bit A-law */ 327 #define BIT16_LITTLE 0x40 /* 16-bit signed, little endian */ 328 #define BIT8_ULAW 0x20 /* 8-bit mu-law */ 329 #define BIT8_LINEAR 0x00 /* 8-bit unsigned */ 330 #define REC_DFORMAT 0x1C 331 #define PLAY_DFORMAT 0x08 332 #define DMA_ACCESS 0x00 333 #define PIO_ACCESS 0xC0 334 #define DMA_SIMPLEX 0x04 335 #define STEREO 0x10 /* CxDFI[4] */ 336 #define AUTOCALIB 0x08 /* CFIG1I[3] */ 337 #define ROM_IO 0x02 /* ROM I/O cycles - LMCI[1]=1 */ 338 #define DRAM_IO 0x4D /* DRAM I/O cycles - LMCI[1]=0 */ 339 #define AUTOI 0x01 /* LMCI[0]=1 */ 340 #define PLDNI 0x07 341 #define ACTIVATE_DEV 0x30 342 #define PWAKEI 0x03 /* Index for PWAKEI */ 343 #define PISOCI 0x01 /* Index for PISOCI */ 344 #define PSECI 0xF1 /* Index for PSECI */ 345 #define RANGE_IOCHK 0x31 /* PURCI or PRRCI Index */ 346 #define MIDI_RESET 0x03 347 348 #define IW_DMA_RECORD 0x02 349 #define IW_DMA_PLAYBACK 0x01 350 351 #define IW_MCE 0x40 352 353 #define IN 0 354 #define OUT 1 355 356 /* codec indirect register access */ 357 358 #define IW_WRITE_CODEC_1(reg, val) \ 359 do {\ 360 bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, (u_char)(reg));\ 361 bus_space_write_1(sc->sc_iot, sc->codec_index_h, sc->cdatap, (u_char)val);\ 362 bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, 0);\ 363 } while (0)\ 364 365 #define IW_READ_CODEC_1(reg, ret) \ 366 do {\ 367 bus_space_write_1(sc->sc_iot, sc->codec_index_h, sc->codec_index, (u_char)(reg));\ 368 ret = bus_space_read_1(sc->sc_iot, sc->codec_index_h, sc->cdatap);\ 369 bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, 0);\ 370 } while (0)\ 371 372 /* iw direct register access */ 373 374 #define IW_WRITE_DIRECT_1(reg, h, val) \ 375 do {\ 376 bus_space_write_1(sc->sc_iot, h, reg, (u_char)val);\ 377 } while (0)\ 378 379 #define IW_READ_DIRECT_1(reg, h, ret) \ 380 do {\ 381 ret = bus_space_read_1(sc->sc_iot, h, (u_char)reg);\ 382 } while (0)\ 383 384 /* general indexed regs access */ 385 386 #define IW_WRITE_GENERAL_1(reg, val) \ 387 do {\ 388 bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\ 389 bus_space_write_1(sc->sc_iot, sc->p3xr_h, 5, (u_char)val);\ 390 } while (0)\ 391 392 #define IW_WRITE_GENERAL_2(reg, val) \ 393 do {\ 394 bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\ 395 bus_space_write_2(sc->sc_iot, sc->p3xr_h, 4, (u_short)val);\ 396 } while (0)\ 397 398 #define IW_READ_GENERAL_1(reg, ret) \ 399 do{\ 400 bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\ 401 ret = bus_space_read_1(sc->sc_iot, sc->p3xr_h, 5);\ 402 } while (0)\ 403 404 #define IW_READ_GENERAL_2(reg, ret) \ 405 do{\ 406 bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\ 407 ret = bus_space_read_2(sc->sc_iot, sc->p3xr_h, 4);\ 408 } while (0)\ 409 410 411 #endif /* INTERWAVEREG_H */ 412