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/netbsd/src/external/gpl3/binutils/dist/gas/config/
Dtc-mep.h94 #define VLIW 1 macro
Dtc-mep.c1239 if (mode == VLIW) in md_assemble()
2148 mode = VLIW; in mep_switch_to_vliw_mode()
2189 if (mode == VLIW) in mep_cleanup()
2196 if (mode == VLIW) in mep_flush_pending_output()
/netbsd/src/external/gpl3/gdb/dist/cpu/
Dmep.opc84 /* A mask for all ISAs executed by a VLIW coprocessor. */
1112 buflength = 4; /* VLIW insn spans 4 bytes. */
1187 buflength = 8; /* VLIW insn spans 8 bytes. */
1344 buflength = 8; /* VLIW insn spans 8 bytes. */
1443 use COP32 to flag those, and COP64 for the VLIW ones,
1676 /* If we're assembling VLIW packets, ignore the 12-bit BSR as we
Dmep-core.cpu1803 (set-psw.om 1) ;; enter VLIW mode
1806 ;; VLIW mode
1845 (set-psw.om 1) ;; enter VLIW mode
1848 ;; VLIW mode
1851 (set-psw.om 0) ;; enter VLIW mode
1985 ;; return in VLIW operation mode
1996 ;; return in VLIW mode
2007 ;; VLIW operation mode
2937 (set-psw.om 1)) ;; to VLIW operation mode
2966 (set-psw.om 1)) ;; to VLIW operation mode
Dfrv.opc843 /* Add in insn to the VLIW vliw if possible.
/netbsd/src/external/gpl3/binutils/dist/cpu/
Dmep.opc84 /* A mask for all ISAs executed by a VLIW coprocessor. */
1110 buflength = 4; /* VLIW insn spans 4 bytes. */
1185 buflength = 8; /* VLIW insn spans 8 bytes. */
1342 buflength = 8; /* VLIW insn spans 8 bytes. */
1441 use COP32 to flag those, and COP64 for the VLIW ones,
1674 /* If we're assembling VLIW packets, ignore the 12-bit BSR as we
Dmep-core.cpu1803 (set-psw.om 1) ;; enter VLIW mode
1806 ;; VLIW mode
1845 (set-psw.om 1) ;; enter VLIW mode
1848 ;; VLIW mode
1851 (set-psw.om 0) ;; enter VLIW mode
1985 ;; return in VLIW operation mode
1996 ;; return in VLIW mode
2007 ;; VLIW operation mode
2937 (set-psw.om 1)) ;; to VLIW operation mode
2966 (set-psw.om 1)) ;; to VLIW operation mode
Dfrv.opc843 /* Add in insn to the VLIW vliw if possible.
/netbsd/src/external/bsd/file/dist/magic/magdir/
Delf240 >18 leshort 160 STMicroelectronics 64bit VLIW DSP,
312 >18 leshort 256 Kalray VLIW core of the MPPA family,
/netbsd/src/external/gpl3/gcc/dist/gcc/config/mips/
Dsr71k.md33 ;; buffering is done via a VLIW dispatch style (with a packing of 6 insns);
122 ;; Simulate a 6 insn VLIW dispatch, 1 cycle in dispatch followed by
/netbsd/src/external/gpl3/binutils/dist/gas/doc/
Dc-tilepro.texi45 which the assembler is free to combine into VLIW bundles, or specify
46 the VLIW bundles explicitly.
Dc-tilegx.texi61 which the assembler is free to combine into VLIW bundles, or specify
62 the VLIW bundles explicitly.
Dc-d10v.texi260 @cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications}
Dc-d30v.texi295 @cite{D30V Architecture: A VLIW Microprocessor for Multimedia Applications}
/netbsd/src/external/gpl3/gcc/dist/gcc/config/frv/
Dfrv.opt203 Pack VLIW instructions.
Dfrv.md143 ;; Note that VLIW packets execute strictly in parallel. Every instruction
150 ;; Three gcc passes are involved in generating VLIW packets:
2510 ;; VLIW instruction.
5455 ;; point. Note, type unknown is used to make sure the VLIW instructions are
/netbsd/src/external/lgpl3/gmp/dist/mpn/powerpc64/
DREADME98 This is a very odd pipeline, it is basically a VLIW masquerading as a plain
/netbsd/src/external/gpl3/gcc/dist/gcc/config/i386/
Dpentium.md73 ;; are always issued together, much like on VLIW.
/netbsd/src/external/gpl3/gdb/dist/sim/frv/
DChangeLog-20211484 VLIW insn and instructions per cycle. Also tabulate the number of insns
1485 in each type of VLIW slot.
2960 * mloop.in (main loop): Update PCSR with address of next VLIW insn
2973 * mloop.in: Only take the first branch in a VLIW insn. Set LR to the
2974 address of the next VLIW insn if flag is set.
/netbsd/src/external/gpl3/binutils/dist/bfd/doc/
Darchures.texi484 bfd_arch_kvx, /* Kalray VLIW core of the MPPA processor family */
/netbsd/src/external/gpl3/gcc/dist/gcc/
Drtl.def1096 after slot0 reservation for a VLIW processor. We could describe it
1140 reserved after slot1 or slot2 reservation for a VLIW processor. We
Dtarget.def1047 combine two small instructions together on @samp{VLIW} machines).\n\
1122 simplify the automaton pipeline description for some @acronym{VLIW}\n\
1178 @acronym{VLIW} processor, the code could actually solve the problem of\n\
1179 packing simple insns into the @acronym{VLIW} insn. Of course, if the\n\
1180 rules of @acronym{VLIW} packing are described in the automaton.\n\
/netbsd/src/external/gpl3/gcc/dist/gcc/config/ia64/
Ditanium2.md51 after slot0 reservation for a VLIW processor. We could describe
93 reserved after slot1 or slot2 reservation for a VLIW processor.
/netbsd/src/external/gpl3/gcc/dist/gcc/doc/
Dmd.texi10330 @cindex VLIW
10333 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
10441 @acronym{VLIW} insn templates).
10606 @cindex VLIW
10609 @acronym{VLIW} processors, or more precisely, to describe a placement
10610 of small instructions into @acronym{VLIW} instruction slots. They
10640 for description that @acronym{VLIW} @samp{slot1} is reserved after
10684 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
/netbsd/src/share/misc/
Dacronyms.comp1883 VLIW very long instruction word

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