1 /* $NetBSD: if_jmereg.h,v 1.8 2024/02/09 22:08:36 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.3 2008/09/22 06:17:21 yongari Exp $ 30 */ 31 32 #ifndef _IF_JMEREG_H 33 #define _IF_JMEREG_H 34 35 /* 36 * JMC250 PCI revisions 37 */ 38 #define DEVICEREVID_JMC250_A0 0x00 39 #define DEVICEREVID_JMC250_A2 0x11 40 41 /* 42 * JMC260 PCI revisions 43 */ 44 #define DEVICEREVID_JMC260_A0 0x00 45 46 /* JMC250 PCI configuration register. */ 47 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */ 48 49 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ 50 51 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 52 53 #define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 54 55 #define JME_PCI_EROM 0x30 56 57 #define JME_PCI_DBG 0x9C 58 59 #define JME_PCI_SPI 0xB0 60 61 #define SPI_ENB 0x00000010 62 #define SPI_SO_STATUS 0x00000008 63 #define SPI_SI_CTRL 0x00000004 64 #define SPI_SCK_CTRL 0x00000002 65 #define SPI_CS_N_CTRL 0x00000001 66 67 #define JME_PCI_PHYCFG0 0xC0 68 69 #define JME_PCI_PHYCFG1 0xC4 70 71 #define JME_PCI_PHYCFG2 0xC8 72 73 #define JME_PCI_PHYCFG3 0xCC 74 75 #define JME_PCI_PIPECTL1 0xD0 76 77 #define JME_PCI_PIPECTL2 0xD4 78 79 /* PCIe link error/status. */ 80 #define JME_PCI_LES 0xD8 81 82 /* proprietary register 0. */ 83 #define JME_PCI_PE0 0xE0 84 #define PE0_SPI_EXIST 0x00200000 85 #define PE0_PME_D0 0x00100000 86 #define PE0_PME_D3H 0x00080000 87 #define PE0_PME_SPI_PAD 0x00040000 88 #define PE0_MASK_ASPM 0x00020000 89 #define PE0_EEPROM_RW_DIS 0x00008000 90 #define PE0_PCI_INTA 0x00001000 91 #define PE0_PCI_INTB 0x00002000 92 #define PE0_PCI_INTC 0x00003000 93 #define PE0_PCI_INTD 0x00004000 94 #define PE0_PCI_SVSSID_WR_ENB 0x00000800 95 #define PE0_MSIX_SIZE_8 0x00000700 96 #define PE0_MSIX_SIZE_7 0x00000600 97 #define PE0_MSIX_SIZE_6 0x00000500 98 #define PE0_MSIX_SIZE_5 0x00000400 99 #define PE0_MSIX_SIZE_4 0x00000300 100 #define PE0_MSIX_SIZE_3 0x00000200 101 #define PE0_MSIX_SIZE_2 0x00000100 102 #define PE0_MSIX_SIZE_1 0x00000000 103 #define PE0_MSIX_SIZE_DEF 0x00000700 104 #define PE0_MSIX_CAP_DIS 0x00000080 105 #define PE0_MSI_PVMC_ENB 0x00000040 106 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 107 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 108 #define PE0_PM_AUXC_MASK 0x00000007 109 #define PE0_PM_AUXC_DEF 0x00000007 110 111 #define JME_PCI_PE1 0xE4 112 113 #define JME_PCI_PHYTEST 0xF8 114 115 #define JME_PCI_GPR 0xFC 116 117 /* 118 * JMC Register Map. 119 * ----------------------------------------------------------------------- 120 * Register Size IO space Memory space 121 * ----------------------------------------------------------------------- 122 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 123 * BAR1 + 0x7F BAR0 + 0x7F 124 * ----------------------------------------------------------------------- 125 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 126 * BAR2 + 0x7F BAR0 + 0x47F 127 * ----------------------------------------------------------------------- 128 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 129 * BAR2 + 0xfF BAR0 + 0x87F 130 * ----------------------------------------------------------------------- 131 * We use bus_space_subregion() to get handle for the 3 different 132 * register space. Register address are relative to the base of each 133 * region. 134 */ 135 136 /* Tx control and status. */ 137 #define JME_TXCSR 0x0000 138 #define TXCSR_QWEIGHT_MASK 0x0F000000 139 #define TXCSR_QWEIGHT_SHIFT 24 140 #define TXCSR_TXQ_SEL_MASK 0x00070000 141 #define TXCSR_TXQ_SEL_SHIFT 16 142 #define TXCSR_TXQ_START 0x00000001 143 #define TXCSR_TXQ_START_SHIFT 8 144 #define TXCSR_FIFO_THRESH_4QW 0x00000000 145 #define TXCSR_FIFO_THRESH_8QW 0x00000040 146 #define TXCSR_FIFO_THRESH_12QW 0x00000080 147 #define TXCSR_FIFO_THRESH_16QW 0x000000C0 148 #define TXCSR_DMA_SIZE_64 0x00000000 149 #define TXCSR_DMA_SIZE_128 0x00000010 150 #define TXCSR_DMA_SIZE_256 0x00000020 151 #define TXCSR_DMA_SIZE_512 0x00000030 152 #define TXCSR_DMA_BURST 0x00000004 153 #define TXCSR_TX_SUSPEND 0x00000002 154 #define TXCSR_TX_ENB 0x00000001 155 #define TXCSR_TXQ0 0 156 #define TXCSR_TXQ1 1 157 #define TXCSR_TXQ2 2 158 #define TXCSR_TXQ3 3 159 #define TXCSR_TXQ4 4 160 #define TXCSR_TXQ5 5 161 #define TXCSR_TXQ6 6 162 #define TXCSR_TXQ7 7 163 #define TXCSR_TXQ_WEIGHT(x) \ 164 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 165 #define TXCSR_TXQ_WEIGHT_MIN 0 166 #define TXCSR_TXQ_WEIGHT_MAX 15 167 #define TXCSR_TXQ_N_SEL(x) \ 168 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 169 #define TXCSR_TXQ_N_START(x) \ 170 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 171 172 /* Tx queue descriptor base address. 16bytes alignment required. */ 173 #define JME_TXDBA_LO 0x0004 174 #define JME_TXDBA_HI 0x0008 175 176 /* Tx queue descriptor count. multiple of 16(max = 1024). */ 177 #define JME_TXQDC 0x000C 178 #define TXQDC_MASK 0x0000007F0 179 180 /* Tx queue next descriptor address. */ 181 #define JME_TXNDA 0x0010 182 #define TXNDA_ADDR_MASK 0xFFFFFFF0 183 #define TXNDA_DESC_EMPTY 0x00000008 184 #define TXNDA_DESC_VALID 0x00000004 185 #define TXNDA_DESC_WAIT 0x00000002 186 #define TXNDA_DESC_FETCH 0x00000001 187 188 /* Tx MAC control ans status. */ 189 #define JME_TXMAC 0x0014 190 #define TXMAC_IFG2_MASK 0xC0000000 191 #define TXMAC_IFG2_DEFAULT 0x40000000 192 #define TXMAC_IFG1_MASK 0x30000000 193 #define TXMAC_IFG1_DEFAULT 0x20000000 194 #define TXMAC_THRESH_1_PKT 0x00000300 195 #define TXMAC_THRESH_1_2_PKT 0x00000200 196 #define TXMAC_THRESH_1_4_PKT 0x00000100 197 #define TXMAC_THRESH_1_8_PKT 0x00000000 198 #define TXMAC_FRAME_BURST 0x00000080 199 #define TXMAC_CARRIER_EXT 0x00000040 200 #define TXMAC_IFG_ENB 0x00000020 201 #define TXMAC_BACKOFF 0x00000010 202 #define TXMAC_CARRIER_SENSE 0x00000008 203 #define TXMAC_COLL_ENB 0x00000004 204 #define TXMAC_CRC_ENB 0x00000002 205 #define TXMAC_PAD_ENB 0x00000001 206 207 /* Tx pause frame control. */ 208 #define JME_TXPFC 0x0018 209 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 210 #define TXPFC_VLAN_TAG_SHIFT 16 211 #define TXPFC_VLAN_ENB 0x00008000 212 #define TXPFC_PAUSE_ENB 0x00000001 213 214 /* Tx timer/retry at half duplex. */ 215 #define JME_TXTRHD 0x001C 216 #define TXTRHD_RT_PERIOD_ENB 0x80000000 217 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 218 #define TXTRHD_RT_PERIOD_SHIFT 8 219 #define TXTRHD_RT_LIMIT_ENB 0x00000080 220 #define TXTRHD_RT_LIMIT_MASK 0x0000007F 221 #define TXTRHD_RT_LIMIT_SHIFT 0 222 #define TXTRHD_RT_PERIOD_DEFAULT 8192 223 #define TXTRHD_RT_LIMIT_DEFAULT 8 224 225 /* Rx control & status. */ 226 #define JME_RXCSR 0x0020 227 #define RXCSR_FIFO_FTHRESH_16T 0x00000000 228 #define RXCSR_FIFO_FTHRESH_32T 0x10000000 229 #define RXCSR_FIFO_FTHRESH_64T 0x20000000 230 #define RXCSR_FIFO_FTHRESH_128T 0x30000000 231 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 232 #define RXCSR_FIFO_THRESH_16QW 0x00000000 233 #define RXCSR_FIFO_THRESH_32QW 0x04000000 234 #define RXCSR_FIFO_THRESH_64QW 0x08000000 235 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 236 #define RXCSR_FIFO_THRESH_MASK 0x0C000000 237 #define RXCSR_DMA_SIZE_16 0x00000000 238 #define RXCSR_DMA_SIZE_32 0x01000000 239 #define RXCSR_DMA_SIZE_64 0x02000000 240 #define RXCSR_DMA_SIZE_128 0x03000000 241 #define RXCSR_RXQ_SEL_MASK 0x00030000 242 #define RXCSR_RXQ_SEL_SHIFT 16 243 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 244 #define RXCSR_DESC_RT_GAP_SHIFT 12 245 #define RXCSR_DESC_RT_GAP_256 0x00000000 246 #define RXCSR_DESC_RT_GAP_512 0x00001000 247 #define RXCSR_DESC_RT_GAP_1024 0x00002000 248 #define RXCSR_DESC_RT_GAP_2048 0x00003000 249 #define RXCSR_DESC_RT_GAP_4096 0x00004000 250 #define RXCSR_DESC_RT_GAP_8192 0x00005000 251 #define RXCSR_DESC_RT_GAP_16384 0x00006000 252 #define RXCSR_DESC_RT_GAP_32768 0x00007000 253 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 254 #define RXCSR_DESC_RT_CNT_SHIFT 8 255 #define RXCSR_PASS_WAKEUP_PKT 0x00000040 256 #define RXCSR_PASS_MAGIC_PKT 0x00000020 257 #define RXCSR_PASS_RUNT_PKT 0x00000010 258 #define RXCSR_PASS_BAD_PKT 0x00000008 259 #define RXCSR_RXQ_START 0x00000004 260 #define RXCSR_RX_SUSPEND 0x00000002 261 #define RXCSR_RX_ENB 0x00000001 262 263 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 264 #define RXCSR_RXQ0 0 265 #define RXCSR_RXQ1 1 266 #define RXCSR_RXQ2 2 267 #define RXCSR_RXQ3 3 268 #define RXCSR_DESC_RT_CNT(x) \ 269 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 270 #define RXCSR_DESC_RT_CNT_DEFAULT 32 271 272 /* Rx queue descriptor base address. 16bytes alignment needed. */ 273 #define JME_RXDBA_LO 0x0024 274 #define JME_RXDBA_HI 0x0028 275 276 /* Rx queue descriptor count. multiple of 16(max = 1024). */ 277 #define JME_RXQDC 0x002C 278 #define RXQDC_MASK 0x0000007F0 279 280 /* Rx queue next descriptor address. */ 281 #define JME_RXNDA 0x0030 282 #define RXNDA_ADDR_MASK 0xFFFFFFF0 283 #define RXNDA_DESC_EMPTY 0x00000008 284 #define RXNDA_DESC_VALID 0x00000004 285 #define RXNDA_DESC_WAIT 0x00000002 286 #define RXNDA_DESC_FETCH 0x00000001 287 288 /* Rx MAC control and status. */ 289 #define JME_RXMAC 0x0034 290 #define RXMAC_RSS_UNICAST 0x00000000 291 #define RXMAC_RSS_UNI_MULTICAST 0x00010000 292 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 293 #define RXMAC_RSS_ALLFRAME 0x00030000 294 #define RXMAC_PROMISC 0x00000800 295 #define RXMAC_BROADCAST 0x00000400 296 #define RXMAC_MULTICAST 0x00000200 297 #define RXMAC_UNICAST 0x00000100 298 #define RXMAC_ALLMULTI 0x00000080 299 #define RXMAC_MULTICAST_FILTER 0x00000040 300 #define RXMAC_COLL_DET_ENB 0x00000020 301 #define RXMAC_FC_ENB 0x00000008 302 #define RXMAC_VLAN_ENB 0x00000004 303 #define RXMAC_PAD_10BYTES 0x00000002 304 #define RXMAC_CSUM_ENB 0x00000001 305 306 /* Rx unicast MAC address. */ 307 #define JME_PAR0 0x0038 308 #define JME_PAR1 0x003C 309 310 /* Rx multicast address hash table. */ 311 #define JME_MAR0 0x0040 312 #define JME_MAR1 0x0044 313 314 /* Wakeup frame output data port. */ 315 #define JME_WFODP 0x0048 316 317 /* Wakeup frame output interface. */ 318 #define JME_WFOI 0x004C 319 #define WFOI_MASK_0_31 0x00000000 320 #define WFOI_MASK_31_63 0x00000010 321 #define WFOI_MASK_64_95 0x00000020 322 #define WFOI_MASK_96_127 0x00000030 323 #define WFOI_MASK_SEL 0x00000008 324 #define WFOI_CRC_SEL 0x00000000 325 #define WFOI_WAKEUP_FRAME_MASK 0x00000007 326 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 327 328 /* Station management interface. */ 329 #define JME_SMI 0x0050 330 #define SMI_DATA_MASK 0xFFFF0000 331 #define SMI_DATA_SHIFT 16 332 #define SMI_REG_ADDR_MASK 0x0000F800 333 #define SMI_REG_ADDR_SHIFT 11 334 #define SMI_PHY_ADDR_MASK 0x000007C0 335 #define SMI_PHY_ADDR_SHIFT 6 336 #define SMI_OP_WRITE 0x00000020 337 #define SMI_OP_READ 0x00000000 338 #define SMI_OP_EXECUTE 0x00000010 339 #define SMI_MDIO 0x00000008 340 #define SMI_MDOE 0x00000004 341 #define SMI_MDC 0x00000002 342 #define SMI_MDEN 0x00000001 343 #define SMI_REG_ADDR(x) \ 344 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 345 #define SMI_PHY_ADDR(x) \ 346 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 347 348 /* Global host control. */ 349 #define JME_GHC 0x0054 350 #define GHC_LOOPBACK 0x80000000 351 #define GHC_RESET 0x40000000 352 #define GHC_CLKSRC_10_100 0x00a00000 353 #define GHC_CLKSRC_1000 0x00500000 354 #define GHC_CLKSRC_MASK 0x00f00000 355 #define GHC_FULL_DUPLEX 0x00000040 356 #define GHC_SPEED_UNKNOWN 0x00000000 357 #define GHC_SPEED_10 0x00000010 358 #define GHC_SPEED_100 0x00000020 359 #define GHC_SPEED_1000 0x00000030 360 #define GHC_SPEED_MASK 0x00000030 361 #define GHC_LINK_OFF 0x00000004 362 #define GHC_LINK_ON 0x00000002 363 #define GHC_LINK_STAT_POLLING 0x00000001 364 365 /* Power management control and status. */ 366 #define JME_PMCS 0x0060 367 #define PMCS_WAKEUP_FRAME_7 0x80000000 368 #define PMCS_WAKEUP_FRAME_6 0x40000000 369 #define PMCS_WAKEUP_FRAME_5 0x20000000 370 #define PMCS_WAKEUP_FRAME_4 0x10000000 371 #define PMCS_WAKEUP_FRAME_3 0x08000000 372 #define PMCS_WAKEUP_FRAME_2 0x04000000 373 #define PMCS_WAKEUP_FRAME_1 0x02000000 374 #define PMCS_WAKEUP_FRAME_0 0x01000000 375 #define PMCS_LINK_FAIL 0x00040000 376 #define PMCS_LINK_RISING 0x00020000 377 #define PMCS_MAGIC_FRAME 0x00010000 378 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 379 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 380 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 381 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 382 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 383 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 384 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 385 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 386 #define PMCS_LINK_FAIL_ENB 0x00000004 387 #define PMCS_LINK_RISING_ENB 0x00000002 388 #define PMCS_MAGIC_FRAME_ENB 0x00000001 389 #define PMCS_WOL_ENB_MASK 0x0000FFFF 390 391 392 #define JME_PHY_EEPROM_BASE_MEMOFF 0x0400 393 #define JME_PHY_EEPROM_BASE_IOOFF 0x0000 394 #define JME_PHY_EEPROM_SIZE 0x0080 395 /* Giga PHY & EEPROM registers. */ 396 #define JME_PHY_EEPROM_BASE_ADDR 0x00 397 398 #define JME_GIGAR0LO 0x00 399 #define JME_GIGAR0HI 0x04 400 #define JME_GIGARALO 0x08 401 #define JME_GIGARAHI 0x0C 402 #define JME_GIGARBLO 0x10 403 #define JME_GIGARBHI 0x14 404 #define JME_GIGARCLO 0x18 405 #define JME_GIGARCHI 0x1C 406 #define JME_GIGARDLO 0x20 407 #define JME_GIGARDHI 0x24 408 409 /* BIST status and control. */ 410 #define JME_GIGACSR 0x28 411 #define GIGACSR_STATUS 0x40000000 412 #define GIGACSR_CTRL_MASK 0x30000000 413 #define GIGACSR_CTRL_DEFAULT 0x30000000 414 #define GIGACSR_TX_CLK_MASK 0x0F000000 415 #define GIGACSR_RX_CLK_MASK 0x00F00000 416 #define GIGACSR_TX_CLK_INV 0x00080000 417 #define GIGACSR_RX_CLK_INV 0x00040000 418 #define GIGACSR_PHY_RST 0x00010000 419 #define GIGACSR_IRQ_N_O 0x00001000 420 #define GIGACSR_BIST_OK 0x00000200 421 #define GIGACSR_BIST_DONE 0x00000100 422 #define GIGACSR_BIST_LED_ENB 0x00000010 423 #define GIGACSR_BIST_MASK 0x00000003 424 425 /* PHY Link Status. */ 426 #define JME_LNKSTS 0x30 427 #define LINKSTS_SPEED_10 0x00000000 428 #define LINKSTS_SPEED_100 0x00004000 429 #define LINKSTS_SPEED_1000 0x00008000 430 #define LINKSTS_FULL_DUPLEX 0x00002000 431 #define LINKSTS_PAGE_RCVD 0x00001000 432 #define LINKSTS_SPDDPX_RESOLVED 0x00000800 433 #define LINKSTS_UP 0x00000400 434 #define LINKSTS_ANEG_COMP 0x00000200 435 #define LINKSTS_MDI_CROSSOVR 0x00000040 436 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 437 #define LINKSTS_LPAR_PAUSE 0x00000001 438 439 /* SMB control and status. */ 440 #define JME_SMBCSR 0x40 441 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 442 #define SMBCSR_WR_DATA_NACK 0x00040000 443 #define SMBCSR_CMD_NACK 0x00020000 444 #define SMBCSR_RELOAD 0x00010000 445 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 446 #define SMBCSR_SCL_STAT 0x00000080 447 #define SMBCSR_SDA_STAT 0x00000040 448 #define SMBCSR_EEPROM_PRESENT 0x00000020 449 #define SMBCSR_INIT_LD_DONE 0x00000010 450 #define SMBCSR_HW_BUSY_MASK 0x0000000F 451 #define SMBCSR_HW_IDLE 0x00000000 452 453 /* SMB interface. */ 454 #define JME_SMBINTF 0x44 455 #define SMBINTF_RD_DATA_MASK 0xFF000000 456 #define SMBINTF_RD_DATA_SHIFT 24 457 #define SMBINTF_WR_DATA_MASK 0x00FF0000 458 #define SMBINTF_WR_DATA_SHIFT 16 459 #define SMBINTF_ADDR_MASK 0x0000FF00 460 #define SMBINTF_ADDR_SHIFT 8 461 #define SMBINTF_RD 0x00000020 462 #define SMBINTF_WR 0x00000000 463 #define SMBINTF_CMD_TRIGGER 0x00000010 464 #define SMBINTF_BUSY 0x00000010 465 #define SMBINTF_FAST_MODE 0x00000008 466 #define SMBINTF_GPIO_SCL 0x00000004 467 #define SMBINTF_GPIO_SDA 0x00000002 468 #define SMBINTF_GPIO_ENB 0x00000001 469 470 #define JME_EEPROM_SIG0 0x55 471 #define JME_EEPROM_SIG1 0xAA 472 #define JME_EEPROM_DESC_BYTES 3 473 #define JME_EEPROM_DESC_END 0x80 474 #define JME_EEPROM_FUNC_MASK 0x70 475 #define JME_EEPROM_FUNC_SHIFT 4 476 #define JME_EEPROM_PAGE_MASK 0x0F 477 #define JME_EEPROM_PAGE_SHIFT 0 478 479 #define JME_EEPROM_FUNC0 0 480 /* PCI configuration space. */ 481 #define JME_EEPROM_PAGE_BAR0 0 482 /* 128 bytes I/O window. */ 483 #define JME_EEPROM_PAGE_BAR1 1 484 /* 256 bytes I/O window. */ 485 #define JME_EEPROM_PAGE_BAR2 2 486 487 #define JME_EEPROM_END 0xFF 488 489 #define JME_EEPROM_MKDESC(f, p) \ 490 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 491 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 492 493 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 494 #define JME_EEPINTF 0x48 495 #define EEPINTF_DATA_MASK 0xFFFF0000 496 #define EEPINTF_DATA_SHIFT 16 497 #define EEPINTF_ADDR_MASK 0x0000FC00 498 #define EEPINTF_ADDR_SHIFT 10 499 #define EEPRINTF_OP_MASK 0x00000300 500 #define EEPINTF_OP_EXECUTE 0x00000080 501 #define EEPINTF_DATA_OUT 0x00000008 502 #define EEPINTF_DATA_IN 0x00000004 503 #define EEPINTF_CLK 0x00000002 504 #define EEPINTF_SEL 0x00000001 505 506 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 507 #define JME_EEPCSR 0x4C 508 #define EEPCSR_EEPROM_RELOAD 0x00000002 509 #define EEPCSR_EEPROM_PRESENT 0x00000001 510 511 /* Misc registers. */ 512 #define JME_MISC_BASE_MEMOFF 0x800 513 #define JME_MISC_BASE_IOOFF 0x080 514 #define JME_MISC_SIZE 0x080 515 516 /* Timer control and status. */ 517 #define JME_TMCSR 0x00 518 #define TMCSR_SW_INTR 0x80000000 519 #define TMCSR_TIMER_INTR 0x10000000 520 #define TMCSR_TIMER_ENB 0x01000000 521 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 522 523 /* GPIO control and status. */ 524 #define JME_GPIO 0x04 525 #define GPIO_4_SPI_IN 0x80000000 526 #define GPIO_3_SPI_IN 0x40000000 527 #define GPIO_4_SPI_OUT 0x20000000 528 #define GPIO_4_SPI_OUT_ENB 0x10000000 529 #define GPIO_3_SPI_OUT 0x08000000 530 #define GPIO_3_SPI_OUT_ENB 0x04000000 531 #define GPIO_3_4_LED 0x00000000 532 #define GPIO_3_4_GPIO 0x02000000 533 #define GPIO_2_CLKREQN_IN 0x00100000 534 #define GPIO_2_CLKREQN_OUT 0x00040000 535 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 536 #define GPIO_1_LED42_IN 0x00001000 537 #define GPIO_1_LED42_OUT 0x00000400 538 #define GPIO_1_LED42_OUT_ENB 0x00000200 539 #define GPIO_1_LED42_ENB 0x00000100 540 #define GPIO_0_SDA_IN 0x00000010 541 #define GPIO_0_SDA_OUT 0x00000004 542 #define GPIO_0_SDA_OUT_ENB 0x00000002 543 #define GPIO_0_SDA_ENB 0x00000001 544 545 /* General purpose register 0. */ 546 #define JME_GPREG0 0x08 547 #define GPREG0_SH_POST_DW7_DIS 0x80000000 548 #define GPREG0_SH_POST_DW6_DIS 0x40000000 549 #define GPREG0_SH_POST_DW5_DIS 0x20000000 550 #define GPREG0_SH_POST_DW4_DIS 0x10000000 551 #define GPREG0_SH_POST_DW3_DIS 0x08000000 552 #define GPREG0_SH_POST_DW2_DIS 0x04000000 553 #define GPREG0_SH_POST_DW1_DIS 0x02000000 554 #define GPREG0_SH_POST_DW0_DIS 0x01000000 555 #define GPREG0_DMA_RD_REQ_8 0x00000000 556 #define GPREG0_DMA_RD_REQ_6 0x00100000 557 #define GPREG0_DMA_RD_REQ_5 0x00200000 558 #define GPREG0_DMA_RD_REQ_4 0x00300000 559 #define GPREG0_POST_DW0_ENB 0x00040000 560 #define GPREG0_PCC_CLR_DIS 0x00020000 561 #define GPREG0_FORCE_SCL_OUT 0x00010000 562 #define GPREG0_DL_RSTB_DIS 0x00008000 563 #define GPREG0_STICKY_RESET 0x00004000 564 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 565 #define GPREG0_LINK_CHG_POLL 0x00001000 566 #define GPREG0_LINK_CHG_DIRECT 0x00000000 567 #define GPREG0_MSI_GEN_SEL 0x00000800 568 #define GPREG0_SMB_PAD_PU_DIS 0x00000400 569 #define GPREG0_PCC_UNIT_16US 0x00000000 570 #define GPREG0_PCC_UNIT_256US 0x00000100 571 #define GPREG0_PCC_UNIT_US 0x00000200 572 #define GPREG0_PCC_UNIT_MS 0x00000300 573 #define GPREG0_PCC_UNIT_MASK 0x00000300 574 #define GPREG0_INTR_EVENT_ENB 0x00000080 575 #define GPREG0_PME_ENB 0x00000020 576 #define GPREG0_PHY_ADDR_MASK 0x0000001F 577 #define GPREG0_PHY_ADDR_SHIFT 0 578 #define GPREG0_PHY_ADDR 1 579 580 /* General purpose register 1. */ 581 #define JME_GPREG1 0x0C 582 #define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 583 #define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 584 #define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 585 #define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 586 #define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 587 #define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 588 #define GPREG1_INTDLY_MASK 0x00000007 589 590 /* MSIX entry number of interrupt source. */ 591 #define JME_MSINUM_BASE 0x10 592 #define JME_MSINUM_END 0x1F 593 #define MSINUM_MASK 0x7FFFFFFF 594 #define MSINUM_ENTRY_MASK 7 595 #define MSINUM_REG_INDEX(x) ((x) / 8) 596 #define MSINUM_INTR_SOURCE(x, y) \ 597 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 598 #define MSINUM_NUM_INTR_SOURCE 32 599 600 /* Interrupt event status. */ 601 #define JME_INTR_STATUS 0x20 602 #define INTR_SW 0x80000000 603 #define INTR_TIMER 0x40000000 604 #define INTR_LINKCHG 0x20000000 605 #define INTR_PAUSE 0x10000000 606 #define INTR_MAGIC_PKT 0x08000000 607 #define INTR_WAKEUP_PKT 0x04000000 608 #define INTR_RXQ0_COAL_TO 0x02000000 609 #define INTR_RXQ1_COAL_TO 0x01000000 610 #define INTR_RXQ2_COAL_TO 0x00800000 611 #define INTR_RXQ3_COAL_TO 0x00400000 612 #define INTR_TXQ_COAL_TO 0x00200000 613 #define INTR_RXQ0_COAL 0x00100000 614 #define INTR_RXQ1_COAL 0x00080000 615 #define INTR_RXQ2_COAL 0x00040000 616 #define INTR_RXQ3_COAL 0x00020000 617 #define INTR_TXQ_COAL 0x00010000 618 #define INTR_RXQ3_DESC_EMPTY 0x00008000 619 #define INTR_RXQ2_DESC_EMPTY 0x00004000 620 #define INTR_RXQ1_DESC_EMPTY 0x00002000 621 #define INTR_RXQ0_DESC_EMPTY 0x00001000 622 #define INTR_RXQ3_COMP 0x00000800 623 #define INTR_RXQ2_COMP 0x00000400 624 #define INTR_RXQ1_COMP 0x00000200 625 #define INTR_RXQ0_COMP 0x00000100 626 #define INTR_TXQ7_COMP 0x00000080 627 #define INTR_TXQ6_COMP 0x00000040 628 #define INTR_TXQ5_COMP 0x00000020 629 #define INTR_TXQ4_COMP 0x00000010 630 #define INTR_TXQ3_COMP 0x00000008 631 #define INTR_TXQ2_COMP 0x00000004 632 #define INTR_TXQ1_COMP 0x00000002 633 #define INTR_TXQ0_COMP 0x00000001 634 635 #define INTR_RXQ_COAL_TO \ 636 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 637 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 638 639 #define INTR_RXQ_COAL \ 640 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 641 INTR_RXQ3_COAL) 642 643 #define INTR_RXQ_COMP \ 644 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 645 INTR_RXQ3_COMP) 646 647 #define INTR_RXQ_DESC_EMPTY \ 648 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 649 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 650 651 #define INTR_RXQ_COMP \ 652 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 653 INTR_RXQ3_COMP) 654 655 #define INTR_TXQ_COMP \ 656 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 657 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 658 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 659 660 #define JME_INTRS_ENABLE \ 661 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 662 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 663 664 #define JME_INTRS_CHECK (JME_INTRS_ENABLE | INTR_TXQ_COMP | INTR_RXQ_COMP) 665 666 667 #define N_INTR_SW 31 668 #define N_INTR_TIMER 30 669 #define N_INTR_LINKCHG 29 670 #define N_INTR_PAUSE 28 671 #define N_INTR_MAGIC_PKT 27 672 #define N_INTR_WAKEUP_PKT 26 673 #define N_INTR_RXQ0_COAL_TO 25 674 #define N_INTR_RXQ1_COAL_TO 24 675 #define N_INTR_RXQ2_COAL_TO 23 676 #define N_INTR_RXQ3_COAL_TO 22 677 #define N_INTR_TXQ_COAL_TO 21 678 #define N_INTR_RXQ0_COAL 20 679 #define N_INTR_RXQ1_COAL 19 680 #define N_INTR_RXQ2_COAL 18 681 #define N_INTR_RXQ3_COAL 17 682 #define N_INTR_TXQ_COAL 16 683 #define N_INTR_RXQ3_DESC_EMPTY 15 684 #define N_INTR_RXQ2_DESC_EMPTY 14 685 #define N_INTR_RXQ1_DESC_EMPTY 13 686 #define N_INTR_RXQ0_DESC_EMPTY 12 687 #define N_INTR_RXQ3_COMP 11 688 #define N_INTR_RXQ2_COMP 10 689 #define N_INTR_RXQ1_COMP 9 690 #define N_INTR_RXQ0_COMP 8 691 #define N_INTR_TXQ7_COMP 7 692 #define N_INTR_TXQ6_COMP 6 693 #define N_INTR_TXQ5_COMP 5 694 #define N_INTR_TXQ4_COMP 4 695 #define N_INTR_TXQ3_COMP 3 696 #define N_INTR_TXQ2_COMP 2 697 #define N_INTR_TXQ1_COMP 1 698 #define N_INTR_TXQ0_COMP 0 699 700 /* Interrupt request status. */ 701 #define JME_INTR_REQ_STATUS 0x24 702 703 /* Interrupt enable - setting port. */ 704 #define JME_INTR_MASK_SET 0x28 705 706 /* Interrupt enable - clearing port. */ 707 #define JME_INTR_MASK_CLR 0x2C 708 709 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 710 #define JME_PCCRX0 0x30 711 #define JME_PCCRX1 0x34 712 #define JME_PCCRX2 0x38 713 #define JME_PCCRX3 0x3C 714 #define PCCRX_COAL_TO_MASK 0xFFFF0000 715 #define PCCRX_COAL_TO_SHIFT 16 716 #define PCCRX_COAL_PKT_MASK 0x0000FF00 717 #define PCCRX_COAL_PKT_SHIFT 8 718 719 #define PCCRX_COAL_TO_MIN 1 720 #define PCCRX_COAL_TO_DEFAULT 100 721 #define PCCRX_COAL_TO_MAX 65535 722 723 #define PCCRX_COAL_PKT_MIN 1 724 #define PCCRX_COAL_PKT_DEFAULT 128 725 #define PCCRX_COAL_PKT_MAX 255 726 727 /* Packet completion coalescing control of Tx queue. */ 728 #define JME_PCCTX 0x40 729 #define PCCTX_COAL_TO_MASK 0xFFFF0000 730 #define PCCTX_COAL_TO_SHIFT 16 731 #define PCCTX_COAL_PKT_MASK 0x0000FF00 732 #define PCCTX_COAL_PKT_SHIFT 8 733 #define PCCTX_COAL_TXQ7 0x00000080 734 #define PCCTX_COAL_TXQ6 0x00000040 735 #define PCCTX_COAL_TXQ5 0x00000020 736 #define PCCTX_COAL_TXQ4 0x00000010 737 #define PCCTX_COAL_TXQ3 0x00000008 738 #define PCCTX_COAL_TXQ2 0x00000004 739 #define PCCTX_COAL_TXQ1 0x00000002 740 #define PCCTX_COAL_TXQ0 0x00000001 741 742 #define PCCTX_COAL_TO_MIN 1 743 #define PCCTX_COAL_TO_DEFAULT 100 744 #define PCCTX_COAL_TO_MAX 65535 745 746 #define PCCTX_COAL_PKT_MIN 1 747 #define PCCTX_COAL_PKT_DEFAULT 128 748 #define PCCTX_COAL_PKT_MAX 255 749 750 /* Chip mode and FPGA version. */ 751 #define JME_CHIPMODE 0x44 752 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 753 #define CHIPMODE_FPGA_REV_SHIFT 16 754 #define CHIPMODE_NOT_FPGA 0 755 #define CHIPMODE_REV_MASK 0x0000FF00 756 #define CHIPMODE_REV_SHIFT 8 757 #define CHIPMODE_MODE_48P 0x0000000C 758 #define CHIPMODE_MODE_64P 0x00000004 759 #define CHIPMODE_MODE_128P_MAC 0x00000003 760 #define CHIPMODE_MODE_128P_DBG 0x00000002 761 #define CHIPMODE_MODE_128P_PHY 0x00000000 762 763 /* Shadow status base address high/low. */ 764 #define JME_SHBASE_ADDR_HI 0x48 765 #define JME_SHBASE_ADDR_LO 0x4C 766 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 767 #define SHBASE_POST_FORCE 0x00000002 768 #define SHBASE_POST_ENB 0x00000001 769 770 /* Timer 1 and 2. */ 771 #define JME_TIMER1 0x70 772 #define JME_TIMER2 0x74 773 #define TIMER_ENB 0x01000000 774 #define TIMER_CNT_MASK 0x00FFFFFF 775 #define TIMER_CNT_SHIFT 0 776 #define TIMER_UNIT 1024 /* 1024us */ 777 778 /* Aggressive power mode control. */ 779 #define JME_APMC 0x7C 780 #define APMC_PCIE_SDOWN_STAT 0x80000000 781 #define APMC_PCIE_SDOWN_ENB 0x40000000 782 #define APMC_PSEUDO_HOT_PLUG 0x20000000 783 #define APMC_EXT_PLUGIN_ENB 0x04000000 784 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 785 #define APMC_DIS_SRAM 0x00000004 786 #define APMC_DIS_CLKPM 0x00000002 787 #define APMC_DIS_CLKTX 0x00000001 788 789 /* Packet completion coalescing status of Rx queue 0, 1, 2 and 3. */ 790 #define JME_PCCSRX_BASE 0x80 791 #define JME_PCCSRX_END 0x8F 792 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 793 #define PCCSRX_TO_MASK 0xFFFF0000 794 #define PCCSRX_TO_SHIFT 16 795 #define PCCSRX_PKT_CNT_MASK 0x0000FF00 796 #define PCCSRX_PKT_CNT_SHIFT 8 797 798 /* Packet completion coalescing status of Tx queue. */ 799 #define JME_PCCSTX 0x90 800 #define PCCSTX_TO_MASK 0xFFFF0000 801 #define PCCSTX_TO_SHIFT 16 802 #define PCCSTX_PKT_CNT_MASK 0x0000FF00 803 #define PCCSTX_PKT_CNT_SHIFT 8 804 805 /* Tx queues empty indicator. */ 806 #define JME_TXQEMPTY 0x94 807 #define TXQEMPTY_TXQ7 0x00000080 808 #define TXQEMPTY_TXQ6 0x00000040 809 #define TXQEMPTY_TXQ5 0x00000020 810 #define TXQEMPTY_TXQ4 0x00000010 811 #define TXQEMPTY_TXQ3 0x00000008 812 #define TXQEMPTY_TXQ2 0x00000004 813 #define TXQEMPTY_TXQ1 0x00000002 814 #define TXQEMPTY_TXQ0 0x00000001 815 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 816 817 /* RSS control registers. */ 818 #define JME_RSS_BASE 0x0C00 819 820 #define JME_RSSC 0x0C00 821 #define RSSC_HASH_LEN_MASK 0x0000E000 822 #define RSSC_HASH_64_ENTRY 0x0000A000 823 #define RSSC_HASH_128_ENTRY 0x0000E000 824 #define RSSC_HASH_NONE 0x00001000 825 #define RSSC_HASH_IPV6 0x00000800 826 #define RSSC_HASH_IPV4 0x00000400 827 #define RSSC_HASH_IPV6_TCP 0x00000200 828 #define RSSC_HASH_IPV4_TCP 0x00000100 829 #define RSSC_NCPU_MASK 0x000000F8 830 #define RSSC_NCPU_SHIFT 3 831 #define RSSC_DIS_RSS 0x00000000 832 #define RSSC_2RXQ_ENB 0x00000001 833 #define RSSS_4RXQ_ENB 0x00000002 834 835 /* CPU vector. */ 836 #define JME_RSSCPU 0x0C04 837 #define RSSCPU_N_SEL(x) ((1 << (x)) 838 839 /* RSS Hash value. */ 840 #define JME_RSSHASH 0x0C10 841 842 #define JME_RSSHASH_STAT 0x0C14 843 844 #define JME_RSS_RDATA0 0x0C18 845 846 #define JME_RSS_RDATA1 0x0C1C 847 848 /* RSS secret key. */ 849 #define JME_RSSKEY_BASE 0x0C40 850 #define JME_RSSKEY_LAST 0x0C64 851 #define JME_RSSKEY_END 0x0C67 852 #define HASHKEY_NBYTES 40 853 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 854 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 855 856 /* RSS indirection table entries. */ 857 #define JME_RSSTBL_BASE 0x0C80 858 #define JME_RSSTBL_END 0x0CFF 859 #define RSSTBL_NENTRY 128 860 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 861 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 862 863 /* MSI-X table. */ 864 #define JME_MSIX_BASE_ADDR 0x2000 865 866 #define JME_MSIX_BASE 0x2000 867 #define JME_MSIX_END 0x207F 868 #define JME_MSIX_NENTRY 8 869 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 870 #define MSIX_ADDR_HI_OFF 0x00 871 #define MSIX_ADDR_LO_OFF 0x04 872 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC 873 #define MSIX_DATA_OFF 0x08 874 #define MSIX_VECTOR_OFF 0x0C 875 #define MSIX_VECTOR_RSVD 0x80000000 876 #define MSIX_VECTOR_DIS 0x00000001 877 878 /* MSI-X PBA. */ 879 #define JME_MSIX_PBA_BASE_ADDR 0x3000 880 881 #define JME_MSIX_PBA 0x3000 882 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 883 #define MSIX_PBA_RSVD_SHIFT 8 884 #define MSIX_PBA_PEND_MASK 0x000000FF 885 #define MSIX_PBA_PEND_SHIFT 0 886 #define MSIX_PBA_PEND_ENTRY7 0x00000080 887 #define MSIX_PBA_PEND_ENTRY6 0x00000040 888 #define MSIX_PBA_PEND_ENTRY5 0x00000020 889 #define MSIX_PBA_PEND_ENTRY4 0x00000010 890 #define MSIX_PBA_PEND_ENTRY3 0x00000008 891 #define MSIX_PBA_PEND_ENTRY2 0x00000004 892 #define MSIX_PBA_PEND_ENTRY1 0x00000002 893 #define MSIX_PBA_PEND_ENTRY0 0x00000001 894 895 #define JME_PHY_OUI 0x001B8C 896 #define JME_PHY_MODEL 0x21 897 #define JME_PHY_REV 0x01 898 #define JME_PHY_ADDR 1 899 900 /* JMC250 shadow status block. */ 901 struct jme_ssb { 902 uint32_t dw0; 903 uint32_t dw1; 904 uint32_t dw2; 905 uint32_t dw3; 906 uint32_t dw4; 907 uint32_t dw5; 908 uint32_t dw6; 909 uint32_t dw7; 910 }; 911 912 /* JMC250 descriptor structures. */ 913 struct jme_desc { 914 uint32_t flags; 915 uint32_t buflen; 916 uint32_t addr_hi; 917 uint32_t addr_lo; 918 }; 919 920 #define JME_TD_OWN 0x80000000 921 #define JME_TD_INTR 0x40000000 922 #define JME_TD_64BIT 0x20000000 923 #define JME_TD_TCPCSUM 0x10000000 924 #define JME_TD_UDPCSUM 0x08000000 925 #define JME_TD_IPCSUM 0x04000000 926 #define JME_TD_TSO 0x02000000 927 #define JME_TD_VLAN_TAG 0x01000000 928 #define JME_TD_VLAN_MASK 0x0000FFFF 929 930 #define JME_TD_MSS_MASK 0xFFFC0000 931 #define JME_TD_MSS_SHIFT 18 932 #define JME_TD_BUF_LEN_MASK 0x0000FFFF 933 #define JME_TD_BUF_LEN_SHIFT 0 934 935 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF 936 #define JME_TD_FRAME_LEN_SHIFT 0 937 938 /* 939 * Only the first Tx descriptor of a packet is updated 940 * after packet transmission. 941 */ 942 #define JME_TD_TMOUT 0x20000000 943 #define JME_TD_RETRY_EXP 0x10000000 944 #define JME_TD_COLLISION 0x08000000 945 #define JME_TD_UNDERRUN 0x04000000 946 #define JME_TD_EHDR_SIZE_MASK 0x000000FF 947 #define JME_TD_EHDR_SIZE_SHIFT 0 948 949 #define JME_TD_SEG_CNT_MASK 0xFFFF0000 950 #define JME_TD_SEG_CNT_SHIFT 16 951 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF 952 #define JME_TD_RETRY_CNT_SHIFT 0 953 954 #define JME_RD_OWN 0x80000000 955 #define JME_RD_INTR 0x40000000 956 #define JME_RD_64BIT 0x20000000 957 958 #define JME_RD_BUF_LEN_MASK 0x0000FFFF 959 #define JME_RD_BUF_LEN_SHIFT 0 960 961 /* 962 * Only the first Rx descriptor of a packet is updated 963 * after packet reception. 964 */ 965 #define JME_RD_MORE_FRAG 0x20000000 966 #define JME_RD_TCP 0x10000000 967 #define JME_RD_UDP 0x08000000 968 #define JME_RD_IPCSUM 0x04000000 969 #define JME_RD_TCPCSUM 0x02000000 970 #define JME_RD_UDPCSUM 0x01000000 971 #define JME_RD_VLAN_TAG 0x00800000 972 #define JME_RD_IPV4 0x00400000 973 #define JME_RD_IPV6 0x00200000 974 #define JME_RD_PAUSE 0x00100000 975 #define JME_RD_MAGIC 0x00080000 976 #define JME_RD_WAKEUP 0x00040000 977 #define JME_RD_BCAST 0x00030000 978 #define JME_RD_MCAST 0x00020000 979 #define JME_RD_UCAST 0x00010000 980 #define JME_RD_VLAN_MASK 0x0000FFFF 981 #define JME_RD_VLAN_SHIFT 0 982 #define JME_RD_TCPV4 (JME_RD_IPV4|JME_RD_TCP) 983 #define JME_RD_UDPV4 (JME_RD_IPV4|JME_RD_UDP) 984 #define JME_RD_TCPV6 (JME_RD_IPV6|JME_RD_TCP) 985 #define JME_RD_UDPV6 (JME_RD_IPV6|JME_RD_UDP) 986 987 #define JME_RD_VALID 0x80000000 988 #define JME_RD_CNT_MASK 0x7F000000 989 #define JME_RD_CNT_SHIFT 24 990 #define JME_RD_GIANT 0x00800000 991 #define JME_RD_GMII_ERR 0x00400000 992 #define JME_RD_NBL_RCVD 0x00200000 993 #define JME_RD_COLL 0x00100000 994 #define JME_RD_ABORT 0x00080000 995 #define JME_RD_RUNT 0x00040000 996 #define JME_RD_FIFO_OVRN 0x00020000 997 #define JME_RD_CRC_ERR 0x00010000 998 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF 999 1000 #define JME_RX_ERR_STAT \ 1001 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 1002 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 1003 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 1004 1005 #define JME_RD_ERR_MASK 0x00FF0000 1006 #define JME_RD_ERR_SHIFT 16 1007 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 1008 #define JME_RX_ERR_BITS "\20" \ 1009 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 1010 "\5COLL\6NBLRCVD\7GMIIERR\10" 1011 1012 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 1013 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 1014 #define JME_RX_PAD_BYTES 10 1015 1016 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 1017 1018 #define JME_RD_RSS_HASH_MASK 0x00003F00 1019 #define JME_RD_RSS_HASH_SHIFT 8 1020 #define JME_RD_RSS_HASH_NONE 0x00000000 1021 #define JME_RD_RSS_HASH_IPV4 0x00000100 1022 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1023 #define JME_RD_RSS_HASH_IPV6 0x00000400 1024 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1025 #define JME_RD_HASH_FN_NONE 0x00000000 1026 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1027 1028 #define JME_MAX_TX_LEN 65535 1029 #define JME_MAX_RX_LEN 65535 1030 1031 #define JME_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 1032 #define JME_ADDR_HI(x) ((uint64_t) (x) >> 32) 1033 1034 /* 1035 * JMC250 can't handle Tx checksum offload/TSO if frame length 1036 * is larger than its FIFO size(2K). It's also good idea to not 1037 * use jumbo frame if hardware is running at half-duplex media. 1038 * Because the jumbo frame may not fit into the Tx FIFO, 1039 * collisions make hardware fetch frame from host memory with 1040 * DMA again which in turn slows down Tx performance 1041 * significantly. 1042 */ 1043 #define JME_TX_FIFO_SIZE 2000 1044 /* 1045 * JMC250 has just 4K Rx FIFO. To support jumbo frame that is 1046 * larger than 4K bytes in length, Rx FIFO threshold should be 1047 * adjusted to minimize Rx FIFO overrun. 1048 */ 1049 #define JME_RX_FIFO_SIZE 4000 1050 1051 #endif 1052