1 /* $NetBSD: ttwogareg.h,v 1.5 2021/12/05 04:31:06 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Register description for the Digital Equipment Corp. T2 Gate Array, 34 * the CBUS->PCI bridge found in the Sable, Sable-Gamma, and Lynx. 35 * 36 * Note all CBUS registers on the Sable are located in the T2. The 37 * T2 is located at address 3.8E00.0000. 38 */ 39 40 /* 41 * CBUS address bias for the Sable-Gamma and Lynx (EV5) 42 */ 43 #define T2_GAMMA_CBUS_BIAS 0x8000000000UL 44 45 extern bus_addr_t ttwoga_gamma_cbus_bias; 46 47 #define REGVAL(r) (*(volatile uint64_t *) \ 48 ALPHA_PHYS_TO_K0SEG(ttwoga_gamma_cbus_bias + (r))) 49 50 /* 51 * Sable/T2 System Address Map. There is a 34-bit physical address space. 52 * 53 * 0.0000.0000 Physical memory (2G - cached) 54 * 55 * 0.8000.0000 Reserved (2G - cached) 56 * 57 * 1.0000.0000 Allocate invalid (2G - uncached) 58 * 59 * 1.8000.0000 PCI 1 Dense Memory (2G - uncached) 60 * 61 * 2.0000.0000 PCI 0 Sparse Memory (4G - uncached, 128M addressable) 62 * 63 * 3.0000.0000 PCI 1 Sparse Memory (2G - uncached, 64M addressable) 64 * 65 * 3.8000.0000 CBUS CSRs (256M - uncached) 66 * 67 * 3.9000.0000 PCI 0 Configuration (128M - uncached) 68 * 69 * 3.9800.0000 PCI 1 Configuration (128M - uncached) 70 * 71 * 3.a000.0000 PCI 0 Sparse I/O (256M - uncached, 8M addressable) 72 * 73 * 3.b000.0000 PCI 1 Sparse I/O (256M - uncached, 8M addressable) 74 * 75 * 3.c000.0000 PCI 0 Dense Memory (1G - uncached) 76 */ 77 78 #define T2_PCI1_DMEM_BASE 0x180000000UL 79 80 #define T2_PCI0_SMEM_BASE 0x200000000UL 81 82 #define T2_PCI1_SMEM_BASE 0x300000000UL 83 84 #define T2_CBUS_BASE 0x380000000UL 85 86 #define T2_PCI0_CONF_BASE 0x390000000UL 87 88 #define T2_PCI1_CONF_BASE 0x398000000UL 89 90 #define T2_PCI0_SIO_BASE 0x3a0000000UL 91 92 #define T2_PCI1_SIO_BASE 0x3b0000000UL 93 94 #define T2_PCI0_DMEM_BASE 0x3c0000000UL 95 96 97 /* 98 * CBUS address map: 99 * 100 * 3.8000.0000 CPU0 CSRs 101 * 3.8100.0000 CPU1 CSRs 102 * 3.8200.0000 CPU2 CSRs 103 * 3.8300.0000 CPU3 CSRs 104 * 3.8400.0000 reserved 105 * 3.8700.0000 reserved 106 * 3.8800.0000 MEM0 CSRs 107 * 3.8900.0000 MEM1 CSRs 108 * 3.8a00.0000 MEM2 CSRs 109 * 3.8b00.0000 MEM3 CSRs 110 * 3.8c00.0000 reserved 111 * 3.8e00.0000 T2 Gate Array (PCI interface) 112 * 3.8f00.0000 Expansion I/O 113 */ 114 #define T2_CBUS_SLOT_STRIDE 0x01000000UL 115 116 #define T2_CBUS_CPUn_BASE(n) (T2_CBUS_BASE + 0x00000000UL + \ 117 ((n) * T2_CBUS_SLOT_STRIDE)) 118 #if 0 119 #define T2_CBUS_CPU0_BASE (T2_CBUS_BASE + 0x00000000UL) 120 #define T2_CBUS_CPU1_BASE (T2_CBUS_BASE + 0x01000000UL) 121 #define T2_CBUS_CPU2_BASE (T2_CBUS_BASE + 0x02000000UL) 122 #define T2_CBUS_CPU3_BASE (T2_CBUS_BASE + 0x03000000UL) 123 #endif 124 #define T2_CBUS_MEMn_BASE(n) (T2_CBUS_BASE + 0x08000000UL + \ 125 ((n) * T2_CBUS_SLOT_STRIDE)) 126 #if 0 127 #define T2_CBUS_MEM0_BASE (T2_CBUS_BASE + 0x08000000UL) 128 #define T2_CBUS_MEM1_BASE (T2_CBUS_BASE + 0x09000000UL) 129 #define T2_CBUS_MEM2_BASE (T2_CBUS_BASE + 0x0a000000UL) 130 #define T2_CBUS_MEM3_BASE (T2_CBUS_BASE + 0x0b000000UL) 131 #endif 132 #define T2_CBUS_TTWOGA_BASE (T2_CBUS_BASE + 0x0e000000UL) 133 #define T2_CBUS_EXPIO_BASE (T2_CBUS_BASE + 0x0f000000UL) 134 135 136 /* 137 * CBUS CPU module control/status registers. 138 */ 139 #define T2_SABLE_BCC 0x00000000 /* Backup Cache Control */ 140 141 #define T2_SABLE_BCCE 0x00000020 /* Backup Cache Correctable Error */ 142 143 #define T2_SABLE_BCCEA 0x00000040 /* Backup Cache Correctable Error 144 Address (latched) */ 145 146 #define T2_SABLE_BCUE 0x00000080 /* Backup Cache Uncorrectable Error */ 147 148 #define T2_SABLE_BCUEA 0x000000a0 /* Backup Cache Uncorrectable Error 149 Address (latched) */ 150 151 #define T2_SABLE_DTER 0x000000c0 /* Duplicate Tag Error */ 152 153 #define T2_SABLE_CBCTL 0x000000e0 /* CBUS Control */ 154 155 #define T2_SABLE_CBE 0x00000100 /* CBUS Error */ 156 157 #define T2_SABLE_CBEAL 0x00000120 /* CBUS Error Address Low (latched) */ 158 159 #define T2_SABLE_CBEAH 0x00000140 /* CBUS Error Address High (latched) */ 160 161 #define T2_SABLE_PMBX 0x00000180 /* Processor Mailbox */ 162 163 #define T2_SABLE_IPIR 0x000001a0 /* Interprocessor Interrupt Request */ 164 165 #define T2_SABLE_SIC 0x000001c0 /* System Interrupt Clear */ 166 167 #define T2_SABLE_ADLK 0x000001e0 /* Address Lock */ 168 169 #define T2_SABLE_MADRL 0x00000200 /* CBUS Miss Address */ 170 171 #define T2_SABLE_REV 0x00000220 /* CMIC Revision */ 172 173 174 /* 175 * T2 Gate Array control/status registers. 176 */ 177 #define T2_SIZE 0x4e0 178 #define _T2GA(b, r) REGVAL((T2_CBUS_TTWOGA_BASE + (T2_SIZE * (b))) + (r)) 179 #define T2GA(tcp, r) _T2GA((tcp)->tc_hose, (r)) 180 181 #define T2_IOCSR 0x0000UL /* I/O control status */ 182 /* 0x0000000000000001UL must be zero */ 183 #define IOCSR_EL 0x0000000000000002UL /* enable loopback */ 184 #define IOCSR_ESMV 0x0000000000000004UL /* enable state mach. vis. */ 185 #define IOCSR_PDBP 0x0000000000000008UL /* PCI drive bad parity */ 186 #define IOCSR_PCIS0_1 0x0000000000000010UL /* PCI slot 0 present */ 187 #define IOCSR_PCIS0_2 0x0000000000000020UL /* PCI slot 0 present */ 188 #define IOCSR_PINT 0x0000000000000040UL /* PCI interrupt high */ 189 #define IOCSR_ENTLBEC 0x0000000000000080UL /* enable TLB error check */ 190 #define IOCSR_ENCCMDA 0x0000000000000100UL /* enable CXACK check */ 191 /* 0x0000000000000200UL must be zero */ 192 #define IOCSR_ENXXCHG 0x0000000000000400UL /* EV5 excl. exchange enable */ 193 /* 0x0000000000000800UL must be zero */ 194 #define IOCSR_CAWWP0 0x0000000000001000UL /* CBUS c/a wr. wrong parity */ 195 #define IOCSR_CAWWP2 0x0000000000002000UL /* CBUS c/a wr. wrong parity */ 196 #define IOCSR_DWWPE 0x0000000000004000UL /* CBUS d. wr. wrong parity e */ 197 #define IOCSR_PCIS2_2 0x0000000000008000UL /* PCI slot 2 present */ 198 #define IOCSR_PSERR 0x0000000000010000UL /* power supply error */ 199 #define IOCSR_MBA7 0x0000000000020000UL /* ext. MBA<7> asserted */ 200 #define IOCSR_PCIS1_1 0x0000000000040000UL /* PCI slot 1 present */ 201 #define IOCSR_PCIS1_2 0x0000000000080000UL /* PCI slot 1 present */ 202 #define IOCSR_PDWWP1 0x0000000000100000UL /* PCI DMA WWP HW1 */ 203 #define IOCSR_PDWWP0 0x0000000000200000UL /* PCI DMA WWP HW0 */ 204 #define IOCSR_PBR 0x0000000000400000UL /* PCI bus reset */ 205 #define IOCSR_PIR 0x0000000000800000UL /* PCI interface reset */ 206 #define IOCSR_ENCOI 0x0000000001000000UL /* en. ACK,CUCERR, o-o-s */ 207 #define IOCSR_EPMS 0x0000000002000000UL /* enable PCI mem space */ 208 #define IOCSR_ETLB 0x0000000004000000UL /* enable TLB */ 209 #define IOCSR_EACC 0x0000000008000000UL /* en. atomic CBUS cycles */ 210 #define IOCSR_FTLB 0x0000000010000000UL /* flush TLB */ 211 #define IOCSR_ECPC 0x0000000020000000UL /* en. CBUS parity check */ 212 #define IOCSR_CIR 0x0000000040000000UL /* CBUS interface reset */ 213 #define IOCSR_EPL 0x0000000080000000UL /* enable PCI lock */ 214 #define IOCSR_CBBCE 0x0000000100000000UL /* CBUS bk-to-bk cycle en. */ 215 #define IOCSR_TRN 0x0000000e00000000UL /* T2 revision number */ 216 #define IOCSR_TRN_SHIFT 33 217 #define TRN_T3 4 218 #define IOCSR_SMVL 0x0000007000000000UL /* mach. state vis. select */ 219 #define IOCSR_SMVL_SHIFT 36 220 #define SMVL_CBUS_CC 0 /* CBUS cycle counter */ 221 #define SMVL_CBUS_RES 1 /* CBUS responder */ 222 #define SMVL_CBUS_COM 2 /* CBUS commander */ 223 #define SMVL_PCI_COM 3 /* PCI commander */ 224 #define SMVL_PCI_RES 4 /* PCI responder */ 225 #define SMVL_TLB_INV 5 /* TLB invalidate */ 226 #define SMVL_PCI_COR 6 /* PCI corner */ 227 #define SMVL_CBUS_COR 7 /* CBUS corner */ 228 #define IOCSR_PCIS2_2H 0x0000008000000000UL /* PCI slot 2 present */ 229 #define IOCSR_EPR 0x0000010000000000UL /* enable passive release */ 230 /* 0x00000e0000000000UL must be zero */ 231 #define IOCSR_CAWWP1 0x0000100000000000UL /* CBUS c/a wr. wrong parity */ 232 #define IOCSR_CAWWP3 0x0000200000000000UL /* CBUS c/a wr. wrong parity */ 233 #define IOCSR_DWWPO 0x0000400000000000UL /* CBUS data wr. parity odd */ 234 /* 0x000f800000000000UL must be zero */ 235 #define IOCSR_PRM 0x0010000000000000UL /* PCI read multiple */ 236 #define IOCSR_PWM 0x0020000000000000UL /* PCI write multiple */ 237 #define IOCSR_FPRDPED 0x0040000000000000UL /* force PCI RDPE detect */ 238 #define IOCSR_FPADPED 0x0080000000000000UL /* force PCI APE detect */ 239 #define IOCSR_FPWDPED 0x0100000000000000UL /* force PCI WDPE detect */ 240 #define IOCSR_EPNMI 0x0200000000000000UL /* enable PCI NMI */ 241 #define IOCSR_EPDTI 0x0400000000000000UL /* enable PCI DTI */ 242 #define IOCSR_EPSEI 0x0800000000000000UL /* enable PCI SERR */ 243 #define IOCSR_EPPEI 0x1000000000000000UL /* enable PCI PERR */ 244 #define IOCSR_ERDPC 0x2000000000000000UL /* enable PCI RDP */ 245 #define IOCSR_EADPC 0x4000000000000000UL /* enable PCI AP int */ 246 #define IOCSR_EWDPC 0x8000000000000000UL /* enable PCI WDP */ 247 248 249 #define T2_CERR1 0x0020UL /* CBUS error 1 */ 250 #define CERR1_URE 0x0000000000000001UL /* uncorrectable read error */ 251 #define CERR1_NAE 0x0000000000000002UL /* no acknowledge */ 252 #define CERR1_CAPE 0x0000000000000004UL /* cmd addr. parity error */ 253 #define CERR1_MCAPE 0x0000000000000008UL /* missed cmd addr par err */ 254 #define CERR1_RWDPE 0x0000000000000010UL /* resp wr data par err */ 255 #define CERR1_MRWDPE 0x0000000000000020UL /* missed rsp data par err */ 256 #define CERR1_RDPE 0x0000000000000040UL /* read data par error */ 257 #define CERR1_MRDPE 0x0000000000000080UL /* missed read data per err */ 258 #define CERR1_CAPE0 0x0000000000000100UL /* CA par err LW 0 */ 259 #define CERR1_CAPE2 0x0000000000000200UL /* CA par err LW 2 */ 260 #define CERR1_DPE0 0x0000000000000400UL /* data par err LW 0 */ 261 #define CERR1_DPE2 0x0000000000000800UL /* data par err LW 2 */ 262 #define CERR1_DPE4 0x0000000000001000UL /* data par err LW 4 */ 263 #define CERR1_DPE6 0x0000000000002000UL /* data per err LW 6 */ 264 /* 0x000000000000c000UL must be zero */ 265 #define CERR1_CWDP 0x0000000000010000UL /* cmdr wr. data par err */ 266 #define CERR1_BSE 0x0000000000020000UL /* bus sync error */ 267 #define CERR1_IPFNE 0x0000000000040000UL /* invalid PFN */ 268 /* 0x000000fffff80000UL must be zero */ 269 #define CERR1_CAPE1 0x0000010000000000UL /* CA par err LW 1 */ 270 #define CERR1_CAPE3 0x0000020000000000UL /* CA par err LW 3 */ 271 #define CERR1_DPE1 0x0000040000000000UL /* data par err LW 1 */ 272 #define CERR1_DPE3 0x0000080000000000UL /* data par err LW 3 */ 273 #define CERR1_DPE5 0x0000100000000000UL /* data par err LW 5 */ 274 #define CERR1_DPE7 0x0000200000000000UL /* data par err LW 7 */ 275 /* 0xffffc00000000000UL must be zero */ 276 277 278 #define T2_CERR2 0x0040UL /* CBUS error 2 */ 279 /* 280 * These bits correspond to CBUS CAD [63:00] during the 281 * command/address transfer of the failing cycle. 282 */ 283 284 285 #define T2_CERR3 0x0060UL /* CBUS error 3 */ 286 /* 287 * These bits correspond to CBUS CAD [127:64] during the 288 * command/address transfer of the failing cycle. 289 */ 290 291 292 #define T2_PERR1 0x0080UL /* PCI error 1 */ 293 #define PERR1_PWDPE 0x0000000000000001UL /* wr. data par error */ 294 #define PERR1_PAPE 0x0000000000000002UL /* addr par error */ 295 #define PERR1_PRDPE 0x0000000000000004UL /* rd. data par error */ 296 #define PERR1_PPE 0x0000000000000008UL /* parity error */ 297 #define PERR1_PSE 0x0000000000000010UL /* system error */ 298 #define PERR1_PDTE 0x0000000000000020UL /* device timeout error */ 299 #define PERR1_NMI 0x0000000000000040UL /* non-maskable interrupt */ 300 301 302 #define T2_PERR2 0x00a0UL /* PCI error 2 */ 303 #define PERR2_PEA 0x00000000ffffffffUL /* error address */ 304 #define PERR2_PEC 0x0000001f00000000UL /* error command */ 305 #define PERR2_PEC_SHIFT 32 306 307 308 #define T2_PSCR 0x00c0UL /* PCI special cycle */ 309 310 311 #define T2_HAE0_1 0x00e0UL /* High Address Extension 1 */ 312 #define HAE0_1_PUA1 0x000000000000001fUL 313 /* 314 * PCI Upper Address -- PCI_AD<31:27> when accessing the 128M 315 * window of PCI0 Sparse Memory. 316 */ 317 318 319 #define T2_HAE0_2 0x0100UL /* High Address Extension 2 */ 320 #define HAE0_2_PUA2 0x00000000000001ffUL 321 /* 322 * PCI Upper Address -- PCI_AD<31:23> when accessing the 8M 323 * window of PCI0 I/O space. 324 */ 325 326 327 #define T2_HBASE 0x0120UL /* PCI Hole Base */ 328 #define HBASE_PHEA 0x00000000000001ffUL /* hole end */ 329 /* 0x0000000000001e00UL must be zero */ 330 #define HBASE_PHE1 0x0000000000002000UL /* hole enable 1 */ 331 #define HBASE_PHE2 0x0000000000004000UL /* hole enable 2 */ 332 #define HBASE_PHSA 0x0000000000ff8000UL /* hole start */ 333 334 335 #define T2_WBASE1 0x0140UL /* Window Base 1 */ 336 #define WBASEx_PWEA 0x0000000000000fffUL /* window end */ 337 /* 0x000000000003f000UL must be zero */ 338 #define WBASEx_SGE 0x0000000000040000UL /* scatter/gather enable */ 339 #define WBASEx_PWE 0x0000000000080000UL /* PCI window enable */ 340 #define WBASEx_PWSA 0x00000000fff00000UL /* window start */ 341 #define WBASEx_PWxA_SHIFT 20 342 343 344 #define T2_WMASK1 0x0160UL /* Window Mask 1 */ 345 #define WMASKx_PWM 0x000000007ff00000UL /* PCI window mask */ 346 347 348 #define T2_TBASE1 0x0180UL /* Translated Base 1 */ 349 #define TBASEx_TBA 0x000000007ffffe00UL /* translated base address */ 350 351 352 #define T2_WBASE2 0x01a0UL /* Window Base 2 */ 353 354 #define T2_WMASK2 0x01c0UL /* Window Mask 2 */ 355 356 #define T2_TBASE2 0x01e0UL /* Translated Base 2 */ 357 358 #define T2_TLBBR 0x0200UL /* TLB bypass */ 359 #define TLBBR_TLBBV 0x0000000000000001UL /* TLB bypass valid */ 360 #define TLBRR_TLBBD 0x000000000007fffeUL /* TLB bypass data */ 361 362 363 #define T2_IVRPR 0x0220UL /* IVR passive release */ 364 #define IVRPR_PRVECT 0x00000000000000ffUL /* passive release vector */ 365 366 367 #define T2_IVIAR 0x0220UL /* IVR interrupt address (pass 2) */ 368 #define IVIAR_IV 0x0003ffff00000000UL /* interrupt vector address */ 369 370 371 #define T2_HAE0_3 0x0240UL /* High Address Extension 3 (pass 2) */ 372 #define HAE0_3_PCA 0x00000000c0000000UL 373 #define HAE0_3_PCA_SHIFT 30 374 /* 375 * PCI Configuration Address -- PCI_AD<1:0> when accessing 376 * PCI configuration space, used to differentiate between 377 * Type 0 and Type 1 cycles. 378 */ 379 380 381 #define T2_HAE0_4 0x0260UL /* High Address Extension 4 (pass 2) */ 382 #define HAE0_4_PUA1 0x0000000000000003UL 383 /* 384 * PCI Upper Address -- PCI_AD<31:30> when accessing the 1G 385 * window of PCI0 Dense Memory. 386 */ 387 388 389 #define T2_WBASE3 0x0280UL /* Window Base 3 (T3/T4) */ 390 391 #define T2_WMASK3 0x02a0UL /* Window Mask 3 (T3/T4) */ 392 393 #define T2_TBASE3 0x02c0UL /* Translated Base 3 (T3/T4) */ 394 395 /* 0x02e0UL unused */ 396 397 #define T2_TDR0 0x0300UL /* TLB Data 0 */ 398 #define TDRx_TLBTD 0x000000003fffffffUL /* TLB entry tag */ 399 #define TDRx_TLBV 0x0000000100000000UL /* TLB entry valid */ 400 #define TDRx_TLBPFN 0x0003fffe00000000UL /* TLB entry data */ 401 402 403 #define T2_TDR1 0x0320UL /* TLB Data 1 */ 404 405 #define T2_TDR2 0x0340UL /* TLB Data 2 */ 406 407 #define T2_TDR3 0x0360UL /* TLB Data 3 */ 408 409 #define T2_TDR4 0x0380UL /* TLB Data 4 */ 410 411 #define T2_TDR5 0x03a0UL /* TLB Data 5 */ 412 413 #define T2_TDR6 0x03c0UL /* TLB Data 6 */ 414 415 #define T2_TDR7 0x03e0UL /* TLB Data 7 */ 416 417 #define T2_WBASE4 0x0400UL /* Window Base 4 (T3/T4) */ 418 419 #define T2_WMASK4 0x0420UL /* Window Mask 4 (T3/T4) */ 420 421 #define T2_TBASE4 0x0440UL /* Translated Base 4 (T3/T4) */ 422 423 #define T2_AIR 0x0460UL /* Address Indirection (T3/T4) */ 424 425 #define T2_VAR 0x0480UL /* Vector Address (T3/T4) */ 426 427 #define T2_DIR 0x04a0UL /* Data Indirection (T3/T4) */ 428 429 #define T2_ICE 0x04c0UL /* IC enable (T3/T4) */ 430