1 /* $NetBSD: sdmmcreg.h,v 1.35 2024/10/18 11:03:52 jmcneill Exp $ */
2 /* $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #ifndef _SDMMCREG_H_
21 #define _SDMMCREG_H_
22
23 /* MMC commands */ /* response type */
24 #define MMC_GO_IDLE_STATE 0 /* R0 */
25 #define MMC_SEND_OP_COND 1 /* R3 */
26 #define MMC_ALL_SEND_CID 2 /* R2 */
27 #define MMC_SET_RELATIVE_ADDR 3 /* R1 */
28 #define MMC_SWITCH 6 /* R1b */
29 #define MMC_SELECT_CARD 7 /* R1 */
30 #define MMC_SEND_EXT_CSD 8 /* R1 */
31 #define MMC_SEND_CSD 9 /* R2 */
32 #define MMC_SEND_CID 10 /* R2 */
33 #define MMC_STOP_TRANSMISSION 12 /* R1b */
34 #define MMC_SEND_STATUS 13 /* R1 */
35 #define MMC_INACTIVE_STATE 15 /* R0 */
36 #define MMC_SET_BLOCKLEN 16 /* R1 */
37 #define MMC_READ_BLOCK_SINGLE 17 /* R1 */
38 #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */
39 #define MMC_SEND_TUNING_BLOCK 19 /* R1 */
40 #define MMC_SEND_TUNING_BLOCK_HS200 21 /* R1 */
41 #define MMC_SET_BLOCK_COUNT 23 /* R1 */
42 #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */
43 #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */
44 #define MMC_PROGRAM_CSD 27 /* R1 */
45 #define MMC_SET_WRITE_PROT 28 /* R1b */
46 #define MMC_SET_CLR_WRITE_PROT 29 /* R1b */
47 #define MMC_SET_SEND_WRITE_PROT 30 /* R1 */
48 #define MMC_TAG_SECTOR_START 32 /* R1 */
49 #define MMC_TAG_SECTOR_END 33 /* R1 */
50 #define MMC_UNTAG_SECTOR 34 /* R1 */
51 #define MMC_TAG_ERASE_GROUP_START 35 /* R1 */
52 #define MMC_TAG_ERASE_GROUP_END 36 /* R1 */
53 #define MMC_UNTAG_ERASE_GROUP 37 /* R1 */
54 #define MMC_ERASE 38 /* R1b */
55 #define MMC_LOCK_UNLOCK 42 /* R1b */
56 #define MMC_APP_CMD 55 /* R1 */
57 #define MMC_READ_OCR 58 /* R3 */
58
59 /* SD commands */ /* response type */
60 #define SD_SEND_RELATIVE_ADDR 3 /* R6 */
61 #define SD_SEND_SWITCH_FUNC 6 /* R1 */
62 #define SD_SEND_IF_COND 8 /* R7 */
63 #define SD_VOLTAGE_SWITCH 11 /* R1 */
64 #define SD_ERASE_WR_BLK_START 32 /* R1 */
65 #define SD_ERASE_WR_BLK_END 33 /* R1 */
66 #define SD_READ_EXTR_SINGLE 48 /* R1 */
67 #define SD_WRITE_EXTR_SINGLE 49 /* R1 */
68
69 /* SD application commands */ /* response type */
70 #define SD_APP_SET_BUS_WIDTH 6 /* R1 */
71 #define SD_APP_SD_STATUS 13 /* R1 */
72 #define SD_APP_SET_WR_BLK_ERASE_COUNT 23 /* R1 */
73 #define SD_APP_OP_COND 41 /* R3 */
74 #define SD_APP_SEND_SCR 51 /* R1 */
75
76 /* SD extended register argument fields */
77 #define SD_EXTR_MIO (0x1U << 31)
78 #define SD_EXTR_MIO_MEM 0
79 #define SD_EXTR_MIO_IO 1
80 #define SD_EXTR_FNO (0xfU << 27)
81 #define SD_EXTR_MW (1U << 26) /* write only */
82 #define SD_EXTR_ADDR (0x1ffff << 9)
83 #define SD_EXTR_LEN 0x1ff
84
85 /* SD erase arguments */
86 #define SD_ERASE_DISCARD 0x00000001
87 #define SD_ERASE_FULE 0x00000002
88
89 /* OCR bits */
90 #define MMC_OCR_MEM_READY (1U<<31)/* memory power-up status bit */
91 #define MMC_OCR_HCS (1<<30) /* SD only */
92 #define MMC_OCR_ACCESS_MODE_MASK (3<<29) /* MMC only */
93 #define MMC_OCR_ACCESS_MODE_BYTE (0<<29) /* MMC only */
94 #define MMC_OCR_ACCESS_MODE_SECTOR (2<<29) /* MMC only */
95 #define MMC_OCR_S18A (1<<24)
96 #define MMC_OCR_3_5V_3_6V (1<<23)
97 #define MMC_OCR_3_4V_3_5V (1<<22)
98 #define MMC_OCR_3_3V_3_4V (1<<21)
99 #define MMC_OCR_3_2V_3_3V (1<<20)
100 #define MMC_OCR_3_1V_3_2V (1<<19)
101 #define MMC_OCR_3_0V_3_1V (1<<18)
102 #define MMC_OCR_2_9V_3_0V (1<<17)
103 #define MMC_OCR_2_8V_2_9V (1<<16)
104 #define MMC_OCR_2_7V_2_8V (1<<15)
105 #define MMC_OCR_2_6V_2_7V (1<<14)
106 #define MMC_OCR_2_5V_2_6V (1<<13)
107 #define MMC_OCR_2_4V_2_5V (1<<12)
108 #define MMC_OCR_2_3V_2_4V (1<<11)
109 #define MMC_OCR_2_2V_2_3V (1<<10)
110 #define MMC_OCR_2_1V_2_2V (1<<9)
111 #define MMC_OCR_2_0V_2_1V (1<<8)
112 #define MMC_OCR_1_65V_1_95V (1<<7)
113
114 /* R1 response type bits */
115 #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */
116 #define MMC_R1_SWITCH_ERROR (1<<7) /* switch command failed */
117 #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */
118
119 /* 48-bit response decoding (32 bits w/o CRC) */
120 #define MMC_R1(resp) ((resp)[0])
121 #define MMC_R3(resp) ((resp)[0])
122 #define SD_R6(resp) ((resp)[0])
123 #define MMC_R7(resp) ((resp)[0])
124 #define MMC_SPI_R1(resp) ((resp)[0])
125 #define MMC_SPI_R7(resp) ((resp)[1])
126
127 /* RCA argument and response */
128 #define MMC_ARG_RCA(rca) ((rca) << 16)
129 #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16)
130
131 /* bus width argument */
132 #define SD_ARG_BUS_WIDTH_1 0
133 #define SD_ARG_BUS_WIDTH_4 2
134
135 /* EXT_CSD fields */
136 #define EXT_CSD_FLUSH_CACHE 32 /* W/E_P */
137 #define EXT_CSD_CACHE_CTRL 33 /* R/W/E_P */
138 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
139 #define EXT_CSD_BUS_WIDTH 183 /* W/E_P */
140 #define EXT_CSD_HS_TIMING 185 /* R/W/E_P */
141 #define EXT_CSD_REV 192 /* R */
142 #define EXT_CSD_STRUCTURE 194 /* R */
143 #define EXT_CSD_CARD_TYPE 196 /* R */
144 #define EXT_CSD_SEC_COUNT 212 /* R */
145 #define EXT_CSD_CACHE_SIZE 249 /* R (4 bytes) */
146
147 /* EXT_CSD field definitions */
148 #define EXT_CSD_CMD_SET_NORMAL (1U << 0)
149 #define EXT_CSD_CMD_SET_SECURE (1U << 1)
150 #define EXT_CSD_CMD_SET_CPSECURE (1U << 2)
151
152 /* EXT_CSD_FLUSH_CACHE */
153 #define EXT_CSD_FLUSH_CACHE_FLUSH (1U << 0)
154 #define EXT_CSD_FLUSH_CACHE_BARRIER (1U << 1)
155
156 /* EXT_CSD_CACHE_CTRL */
157 #define EXT_CSD_CACHE_CTRL_CACHE_EN (1U << 0)
158
159 /* EXT_CSD_BUS_WIDTH */
160 #define EXT_CSD_BUS_WIDTH_1 0 /* 1 bit mode */
161 #define EXT_CSD_BUS_WIDTH_4 1 /* 4 bit mode */
162 #define EXT_CSD_BUS_WIDTH_8 2 /* 8 bit mode */
163 #define EXT_CSD_BUS_WIDTH_4_DDR 5 /* 4 bit mode (DDR) */
164 #define EXT_CSD_BUS_WIDTH_8_DDR 6 /* 8 bit mode (DDR) */
165
166 /* EXT_CSD_HS_TIMING */
167 #define EXT_CSD_HS_TIMING_LEGACY 0
168 #define EXT_CSD_HS_TIMING_HIGHSPEED 1
169 #define EXT_CSD_HS_TIMING_HS200 2
170 #define EXT_CSD_HS_TIMING_HS400 3
171
172 /* EXT_CSD_STRUCTURE */
173 #define EXT_CSD_STRUCTURE_VER_1_0 0 /* CSD Version No.1.0 */
174 #define EXT_CSD_STRUCTURE_VER_1_1 1 /* CSD Version No.1.1 */
175 #define EXT_CSD_STRUCTURE_VER_1_2 2 /* Version 4.1-4.2-4.3 */
176
177 /* EXT_CSD_CARD_TYPE */
178 #define EXT_CSD_CARD_TYPE_F_26M (1 << 0) /* HS 26 MHz */
179 #define EXT_CSD_CARD_TYPE_F_52M (1 << 1) /* HS 52 MHz */
180 #define EXT_CSD_CARD_TYPE_F_DDR52_1_8V (1 << 2) /* HS DDR 52 MHz 1.8V or 3V */
181 #define EXT_CSD_CARD_TYPE_F_DDR52_1_2V (1 << 3) /* HS DDR 52 MHz 1.2V */
182 #define EXT_CSD_CARD_TYPE_F_HS200_1_8V (1 << 4) /* HS200 SDR 200 MHz 1.8V */
183 #define EXT_CSD_CARD_TYPE_F_HS200_1_2V (1 << 5) /* HS200 SDR 200 MHz 1.2V */
184 #define EXT_CSD_CARD_TYPE_F_HS400_1_8V (1 << 6) /* HS400 DDR 200 MHz 1.8V */
185 #define EXT_CSD_CARD_TYPE_F_HS400_1_2V (1 << 7) /* HS400 DDR 200 MHz 1.2V */
186
187 /* EXT_CSD_RST_N_FUNCTION */
188 #define EXT_CSD_RST_N_TMP_DISABLED 0x00
189 #define EXT_CSD_RST_N_PERM_ENABLED 0x01
190 #define EXT_CSD_RST_N_PERM_DISABLED 0x02
191 #define EXT_CSD_RST_N_MASK 0x03
192
193 /* MMC_SWITCH access mode */
194 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
195 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */
196 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */
197 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
198
199 /* SPI mode reports R1/R2(SEND_STATUS) status. */
200 #define R1_SPI_IDLE (1 << 0)
201 #define R1_SPI_ERASE_RESET (1 << 1)
202 #define R1_SPI_ILLEGAL_COMMAND (1 << 2)
203 #define R1_SPI_COM_CRC (1 << 3)
204 #define R1_SPI_ERASE_SEQ (1 << 4)
205 #define R1_SPI_ADDRESS (1 << 5)
206 #define R1_SPI_PARAMETER (1 << 6)
207 /* R1 bit 7 is always zero */
208 #define R2_SPI_CARD_LOCKED (1 << 8)
209 #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
210 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
211 #define R2_SPI_ERROR (1 << 10)
212 #define R2_SPI_CC_ERROR (1 << 11)
213 #define R2_SPI_CARD_ECC_ERROR (1 << 12)
214 #define R2_SPI_WP_VIOLATION (1 << 13)
215 #define R2_SPI_ERASE_PARAM (1 << 14)
216 #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
217 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
218
219 /* MMC R2 response (CSD) */
220 #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
221 #define MMC_CSD_CSDVER_1_0 0
222 #define MMC_CSD_CSDVER_1_1 1
223 #define MMC_CSD_CSDVER_1_2 2 /* MMC 4.1 - 4.2 - 4.3 */
224 #define MMC_CSD_CSDVER_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
225 #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
226 #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */
227 #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */
228 #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */
229 #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */
230 #define MMC_CSD_MMCVER_4_0 4 /* MMC 4.1 - 4.2 - 4.3 */
231 #define MMC_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
232 #define MMC_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 115, 4)
233 #define MMC_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 112, 3)
234 #define MMC_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
235 #define MMC_CSD_TRAN_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
236 #define MMC_CSD_TRAN_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4)
237 #define MMC_CSD_TRAN_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3)
238 #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
239 #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
240 #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \
241 (MMC_CSD_C_SIZE_MULT((resp))+2))
242 #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
243 #define MMC_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
244 #define MMC_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
245
246 /* MMC v1 R2 response (CID) */
247 #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24)
248 #define MMC_CID_PNM_V1_CPY(resp, pnm) \
249 do { \
250 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
251 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
252 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
253 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
254 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
255 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
256 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \
257 (pnm)[7] = '\0'; \
258 } while (/*CONSTCOND*/0)
259 #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8)
260 #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24)
261 #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8)
262
263 /* MMC v2 R2 response (CID) */
264 #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8)
265 #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16)
266 #define MMC_CID_PNM_V2_CPY(resp, pnm) \
267 do { \
268 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
269 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
270 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
271 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
272 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
273 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
274 (pnm)[6] = '\0'; \
275 } while (/*CONSTCOND*/0)
276 #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32)
277
278 /* SD R2 response (CSD) */
279 #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
280 #define SD_CSD_CSDVER_1_0 0
281 #define SD_CSD_CSDVER_2_0 1
282 #define SD_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
283 #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
284 #define SD_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 115, 4)
285 #define SD_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 112, 3)
286 #define SD_CSD_TAAC_1_5_MSEC 0x26
287 #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
288 #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
289 #define SD_CSD_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4)
290 #define SD_CSD_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3)
291 #define SD_CSD_SPEED_25_MHZ 0x32
292 #define SD_CSD_SPEED_50_MHZ 0x5a
293 #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12)
294 #define SD_CSD_CCC_BASIC (1 << 0) /* basic */
295 #define SD_CSD_CCC_BR (1 << 2) /* block read */
296 #define SD_CSD_CCC_BW (1 << 4) /* block write */
297 #define SD_CSD_CCC_ERACE (1 << 5) /* erase */
298 #define SD_CSD_CCC_WP (1 << 6) /* write protection */
299 #define SD_CSD_CCC_LC (1 << 7) /* lock card */
300 #define SD_CSD_CCC_AS (1 << 8) /*application specific*/
301 #define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */
302 #define SD_CSD_CCC_SWITCH (1 << 10) /* switch */
303 #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
304 #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1)
305 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
306 #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1)
307 #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1)
308 #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
309 #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \
310 (SD_CSD_C_SIZE_MULT((resp))+2))
311 #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3)
312 #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3)
313 #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3)
314 #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3)
315 #define SD_CSD_VDD_RW_CURR_100mA 0x7
316 #define SD_CSD_VDD_RW_CURR_80mA 0x6
317 #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22)
318 #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
319 #define SD_CSD_V2_BL_LEN 0x9 /* 512 */
320 #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
321 #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1)
322 #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */
323 #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */
324 #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1)
325 #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
326 #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
327 #define SD_CSD_RW_BL_LEN_2G 0xa
328 #define SD_CSD_RW_BL_LEN_1G 0x9
329 #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1)
330 #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1)
331 #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1)
332 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
333 #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1)
334 #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2)
335
336 /* SD R2 response (CID) */
337 #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8)
338 #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16)
339 #define SD_CID_PNM_CPY(resp, pnm) \
340 do { \
341 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
342 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
343 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
344 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
345 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
346 (pnm)[5] = '\0'; \
347 } while (/*CONSTCOND*/0)
348 #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8)
349 #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32)
350 #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12)
351
352 /* SCR (SD Configuration Register) */
353 #define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4)
354 #define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */
355 #define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4)
356 #define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */
357 #define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */
358 #define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */
359 #define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1)
360 #define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3)
361 #define SCR_SD_SECURITY_NONE 0 /* no security */
362 #define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */
363 #define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */
364 #define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4)
365 #define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */
366 #define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */
367 #define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1)
368 #define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4)
369 #define SCR_SD_SPEC4(scr) MMC_RSP_BITS((scr), 42, 1)
370 #define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 9)
371 #define SCR_CMD_SUPPORT_CMD48(scr) MMC_RSP_BITS((scr), 34, 1)
372 #define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1)
373 #define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1)
374 #define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32)
375
376 /* SSR (SD Status Register) */
377 #define SSR_DAT_BUS_WIDTH(resp) __bitfield((resp), 510, 2)
378 #define SSR_DAT_BUS_WIDTH_1 0
379 #define SSR_DAT_BUS_WIDTH_4 2
380 #define SSR_SECURED_MODE(resp) __bitfield((resp), 509, 1)
381 #define SSR_SD_CARD_TYPE(resp) __bitfield((resp), 480, 16)
382 #define SSR_SD_CARD_TYPE_RDWR 0
383 #define SSR_SD_CARD_TYPE_ROM 1
384 #define SSR_SD_CARD_TYPE_OTP 2
385 #define SSR_SIZE_OF_PROTECTED_AREA(resp) __bitfield((resp), 448, 32)
386 #define SSR_SPEED_CLASS(resp) __bitfield((resp), 440, 8)
387 #define SSR_SPEED_CLASS_0 0
388 #define SSR_SPEED_CLASS_2 1
389 #define SSR_SPEED_CLASS_4 2
390 #define SSR_SPEED_CLASS_6 3
391 #define SSR_SPEED_CLASS_10 4
392 #define SSR_PERFORMANCE_MOVE(resp) __bitfield((resp), 432, 8)
393 #define SSR_AU_SIZE(resp) __bitfield((resp), 428, 4)
394 #define SSR_ERASE_SIZE(resp) __bitfield((resp), 408, 16)
395 #define SSR_ERASE_TIMEOUT(resp) __bitfield((resp), 402, 6)
396 #define SSR_ERASE_OFFSET(resp) __bitfield((resp), 400, 2)
397 #define SSR_UHS_SPEED_GRADE(resp) __bitfield((resp), 396, 4)
398 #define SSR_UHS_SPEED_GRADE_10MB 1
399 #define SSR_UHS_SPEED_GRADE_30MB 3
400 #define SSR_UHS_AU_SIZE(resp) __bitfield((resp), 392, 4)
401 #define SSR_VIDEO_SPEED_CLASS(resp) __bitfield((resp), 384, 8)
402 #define SSR_VSC_AU_SIZE(resp) __bitfield((resp), 368, 10)
403 #define SSR_SUS_ADDR(resp) __bitfield((resp), 346, 22)
404 #define SSR_APP_PERF_CLASS(resp) __bitfield((resp), 336, 4)
405 #define SSR_APP_PERF_CLASS_UNSUPPORTED 0
406 #define SSR_APP_PERF_CLASS_A1 1
407 #define SSR_APP_PERF_CLASS_A2 2
408 #define SSR_PERFORMANCE_ENHANCE(resp) __bitfield((resp), 328, 8)
409 #define SSR_PERFORMANCE_ENHANCE_CACHE __BIT(0)
410 #define SSR_PERFORMANCE_ENHANCE_HOST_MAINT __BIT(1)
411 #define SSR_PERFORMANCE_ENHANCE_CARD_MAINT __BIT(2)
412 #define SSR_PERFORMANCE_ENHANCE_COMMAND_QUEUE __BITS(7,3)
413 #define SSR_DISCARD_SUPPORT(resp) __bitfield((resp), 313, 1)
414 #define SSR_FULE_SUPPORT(resp) __bitfield((resp), 312, 1)
415
416 /* Status of Switch Function */
417 #define SFUNC_STATUS_GROUP(status, group) \
418 (__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16))
419
420 #define SD_ACCESS_MODE_SDR12 0
421 #define SD_ACCESS_MODE_SDR25 1
422 #define SD_ACCESS_MODE_SDR50 2
423 #define SD_ACCESS_MODE_SDR104 3
424 #define SD_ACCESS_MODE_DDR50 4
425
426 /* SD extension data */
427 #define SD_GENERAL_INFO_HDR_REVISION(data) le16dec(&(data)[0])
428 #define SD_GENERAL_INFO_HDR_LENGTH(data) le16dec(&(data)[2])
429 #define SD_GENERAL_INFO_HDR_NUM_EXT(data) ((data)[4])
430 #define SD_GENERAL_INFO_EXT_FIRST 16
431 #define SD_EXTENSION_INFO_SFC(data, index) le16dec(&(data)[(index) + 0])
432 #define SD_EXTENSION_INFO_NEXT(data, index) le16dec(&(data)[(index) + 40])
433 #define SD_EXTENSION_INFO_NUM_REG(data, index) ((data)[(index) + 42])
434 #define SD_EXTENSION_INFO_REG(data, index, num) le32dec(&(data)[(index) + 44 + (num) * 4])
435
436 #define SD_EXTENSION_INFO_REG_FNO(addr) (((addr) >> 18) & 0xf)
437 #define SD_EXTENSION_INFO_REG_START_ADDR(addr) ((addr) & 0x1ffff)
438
439 /* SD extension standard function codes */
440 #define SD_SFC_PEF 0x0002
441
442 /* Performance Enhancement Function */
443 #define SD_PEF_CACHE_SUPPORT(data) ((data)[4] & 0x01)
444 #define SD_PEF_CACHE_ENABLE(data) ((data)[260] & 0x01)
445 #define SD_PEF_CACHE_FLUSH(data) ((data)[261] & 0x01)
446 #define SD_PEF_CACHE_ENABLE_OFFSET 260
447 #define SD_PEF_CACHE_FLUSH_OFFSET 261
448
449 /* This assumes the response fields are in host byte order in 32-bit units. */
450 #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len))
451 static __inline uint32_t
__bitfield(const uint32_t * src,size_t start,size_t len)452 __bitfield(const uint32_t *src, size_t start, size_t len)
453 {
454 if (start + len > 512 || len == 0 || len > 32)
455 return 0;
456
457 src += start / 32;
458 start %= 32;
459
460 uint32_t dst = src[0] >> start;
461
462 if (__predict_false((start + len - 1) / 32 != start / 32)) {
463 dst |= src[1] << (32 - start);
464 }
465
466 return dst & (__BIT(len) - 1);
467 }
468
469 #endif /* _SDMMCREG_H_ */
470