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Searched refs:REG (Results 1 – 25 of 355) sorted by relevance

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/netbsd/src/sys/arch/sh3/sh3/
Ddevreg.c103 SH ## x ## REG(TRA); \
104 SH ## x ## REG(EXPEVT); \
105 SH ## x ## REG(INTEVT); \
107 SH ## x ## REG(BARA); \
108 SH ## x ## REG(BAMRA); \
109 SH ## x ## REG(BASRA); \
110 SH ## x ## REG(BBRA); \
111 SH ## x ## REG(BARB); \
112 SH ## x ## REG(BAMRB); \
113 SH ## x ## REG(BASRB); \
[all …]
/netbsd/src/external/gpl3/binutils/dist/gas/config/
Drx-parse.y145 %type <regno> REG FLAG CREG BCND BMCND SCCND ACC DREG DREGH DREGL DCREG DCMP
149 %token REG FLAG CREG ACC DREG DREGH DREGL DCREG
283 | MOV DOT_B '#' EXPR ',' '[' REG ']'
286 | MOV DOT_W '#' EXPR ',' '[' REG ']'
289 | MOV DOT_L '#' EXPR ',' '[' REG ']'
292 | MOV DOT_B '#' EXPR ',' disp '[' REG ']'
300 | MOV DOT_W '#' EXPR ',' disp '[' REG ']'
306 | MOV DOT_L '#' EXPR ',' disp '[' REG ']'
314 | RTSD '#' EXPR ',' REG '-' REG
323 | CMP REG ',' REG
[all …]
Dbfin-parse.y477 %token REG
604 %type <reg> REG
801 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
831 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
832 COLON expr COMMA REG COLON expr RPAREN aligndir
849 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
850 REG COLON expr RPAREN aligndir
867 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
881 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
894 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
[all …]
Dbfin-lex.l47 [sS][fF][tT][rR][eE][sS][eE][tT] _REG.regno = REG_sftreset; return REG;
48 [oO][mM][oO][dD][eE] _REG.regno = REG_omode; return REG;
49 [iI][dD][lL][eE]_[rR][eE][qQ] _REG.regno = REG_idle_req; return REG;
50 [hH][wW][eE][rR][rR][cC][aA][uU][sS][eE] _REG.regno = REG_hwerrcause; return REG;
51 [eE][xX][cC][aA][uU][sS][eE] _REG.regno = REG_excause; return REG;
52 [eE][mM][uU][cC][aA][uU][sS][eE] _REG.regno = REG_emucause; return REG;
59 [uU][sS][pP] _REG.regno = REG_USP; return REG;
66 [sS][yY][sS][cC][fF][gG] _REG.regno = REG_SYSCFG; return REG;
71 [sS][pP] _REG.regno = REG_SP; return REG;
74 [sS][eE][qQ][sS][tT][aA][tT] _REG.regno = REG_SEQSTAT; return REG;
[all …]
Dbfin-lex.c1115 _REG.regno = REG_sftreset; return REG;
1120 _REG.regno = REG_omode; return REG;
1125 _REG.regno = REG_idle_req; return REG;
1130 _REG.regno = REG_hwerrcause; return REG;
1135 _REG.regno = REG_excause; return REG;
1140 _REG.regno = REG_emucause; return REG;
1175 _REG.regno = REG_USP; return REG;
1210 _REG.regno = REG_SYSCFG; return REG;
1235 _REG.regno = REG_SP; return REG;
1250 _REG.regno = REG_SEQSTAT; return REG;
[all …]
/netbsd/src/usr.sbin/gspa/gspa/
Dgsp_inst.c99 #define EXREG (REG|EXPR)
100 #define EAREG (REG|EA)
101 #define EXAREG (REG|EXPR|EA)
104 #define OPTREG (OPTOPRN|REG)
126 {"ABS", 0x0380, ONEREG, {REG, 0, 0, 0}},
127 {"ADD", 0x4000, ADD, {EXREG, REG, OPTSPEC,0}},
128 {"ADDC",0x4200, TWOREG, {REG, REG, 0, 0}},
129 {"ADDI",0x0B20, IMMREG, {EXPR, REG, OPTSPEC,0}},
130 {"ADDK",0x1000, K32REG, {EXPR, REG, 0, 0}},
131 {"ADDXY",0xE000,TWOREG, {REG, REG, 0, 0}},
[all …]
/netbsd/src/external/gpl3/gdb/dist/sim/rl78/
Dcpu.c63 #define REG(r) ((regbase)->r) macro
103 case RL78_Reg_X: return REG (x); in get_reg()
104 case RL78_Reg_A: return REG (a); in get_reg()
105 case RL78_Reg_C: return REG (c); in get_reg()
106 case RL78_Reg_B: return REG (b); in get_reg()
107 case RL78_Reg_E: return REG (e); in get_reg()
108 case RL78_Reg_D: return REG (d); in get_reg()
109 case RL78_Reg_L: return REG (l); in get_reg()
110 case RL78_Reg_H: return REG (h); in get_reg()
111 case RL78_Reg_AX: return REG (a) * 256 + REG (x); in get_reg()
[all …]
/netbsd/src/sys/arch/luna68k/stand/boot/
Dsio.c107 int rr0 = sioreg(REG(unit, RR0), 0); in siointr()
108 int rr1 = sioreg(REG(unit, RR1), 0); in siointr()
116 sioreg(REG(unit, WR0), WR0_ERRRST); in siointr()
191 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0) in siocnputc()
197 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0) in siocnputc()
216 sioreg(REG(0, WR0), WR0_CHANRST); in sioinit()
224 sioreg(REG(0, WR0), WR0_RSTINT); in sioinit()
226 sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); in sioinit()
228 sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL); in sioinit()
230 sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS); in sioinit()
[all …]
/netbsd/src/sys/dev/tc/
Dsfbplus.c73 #define REG(base, index) *((uint32_t *)(base) + (index)) macro
75 REG(vdac, bt_lo) = ((regno) & 0x00ff); \
76 REG(vdac, bt_hi) = ((regno) & 0x0f00) >> 8; \
611 REG(vdac, bt_reg) = 0x40; /* CMD0 */ tc_wmb(); in bt459init()
612 REG(vdac, bt_reg) = 0x0; /* CMD1 */ tc_wmb(); in bt459init()
613 REG(vdac, bt_reg) = 0xc0; /* CMD2 */ tc_wmb(); in bt459init()
614 REG(vdac, bt_reg) = 0xff; /* PRM */ tc_wmb(); in bt459init()
615 REG(vdac, bt_reg) = 0; /* 205 */ tc_wmb(); in bt459init()
616 REG(vdac, bt_reg) = 0x0; /* PBM */ tc_wmb(); in bt459init()
617 REG(vdac, bt_reg) = 0; /* 207 */ tc_wmb(); in bt459init()
[all …]
Dstic.c117 #define REG(base, index) *((volatile uint32_t *)(base) + (index)) macro
119 REG(vdac, bt_lo) = DUPBYTE0(regno); \
120 REG(vdac, bt_hi) = DUPBYTE1(regno); \
287 REG(vdac, bt_reg) = 0x00c0c0c0; tc_wmb(); in stic_init()
296 REG(vdac, bt_reg) = 0x00000000; tc_wmb(); in stic_init()
297 REG(vdac, bt_reg) = 0x00c2c2c2; tc_wmb(); in stic_init()
298 REG(vdac, bt_reg) = 0x00ffffff; tc_wmb(); in stic_init()
301 REG(vdac, bt_reg) = 0x00000000; in stic_init()
307 REG(vdac, bt_reg) = 0x00ffffff; tc_wmb(); in stic_init()
308 REG(vdac, bt_reg) = 0x00ffffff; tc_wmb(); in stic_init()
[all …]
/netbsd/src/external/gpl3/gdb/dist/opcodes/
Dcr16-opc.c466 #define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE} macro
472 #define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE)
478 REG(r12_L, 12, CR16_R_REGTYPE),
479 REG(r13_L, 13, CR16_R_REGTYPE),
480 REG(ra, 0xe, CR16_R_REGTYPE),
481 REG(sp, 0xf, CR16_R_REGTYPE),
482 REG(sp_L, 0xf, CR16_R_REGTYPE),
483 REG(RA, 0xe, CR16_R_REGTYPE),
494 REG((r12), 0xc, CR16_RP_REGTYPE),
495 REG((r13), 0xd, CR16_RP_REGTYPE),
[all …]
/netbsd/src/external/gpl3/binutils/dist/opcodes/
Dcr16-opc.c466 #define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE} macro
472 #define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE)
478 REG(r12_L, 12, CR16_R_REGTYPE),
479 REG(r13_L, 13, CR16_R_REGTYPE),
480 REG(ra, 0xe, CR16_R_REGTYPE),
481 REG(sp, 0xf, CR16_R_REGTYPE),
482 REG(sp_L, 0xf, CR16_R_REGTYPE),
483 REG(RA, 0xe, CR16_R_REGTYPE),
494 REG((r12), 0xc, CR16_RP_REGTYPE),
495 REG((r13), 0xd, CR16_RP_REGTYPE),
[all …]
/netbsd/src/external/gpl3/gdb/dist/sim/ppc/
Didecode_expression.h271 #define CR_SET(REG, VAL) MBLIT32(CR, REG*4, REG*4+3, VAL) argument
272 #define CR_FIELD(REG) EXTRACTED32(CR, REG*4, REG*4+3) argument
273 #define CR_SET_XER_SO(REG, VAL) \ argument
278 CR_SET(REG, new_bits); \
281 #define CR_COMPARE(REG, LHS, RHS) \ argument
286 CR_SET(REG, new_bits); \
345 #define FPSCR_SET(REG, VAL) MBLIT32(FPSCR, REG*4, REG*4+3, VAL) argument
346 #define FPSCR_FIELD(REG) EXTRACTED32(FPSCR, REG*4, REG*4+3) argument
/netbsd/src/external/gpl3/gcc/dist/libgcc/config/alpha/
Dvms-gcc_shell_handler.c37 typedef unsigned long long REG; typedef
39 #define REG_AT(addr) (*(REG *)(addr))
56 get_dyn_handler_pointer (REG fp) in get_dyn_handler_pointer()
68 REG handler_slot_offset; in get_dyn_handler_pointer()
73 REG handler_data_offset; in get_dyn_handler_pointer()
99 handler_slot_offset = REG_AT ((REG)pd + handler_data_offset); in get_dyn_handler_pointer()
/netbsd/src/external/gpl3/gcc/dist/gcc/config/frv/
Dpredicates.md30 if (GET_CODE (SUBREG_REG (op)) != REG)
36 if (GET_CODE (op) != REG)
56 if (GET_CODE (tmp) == REG
73 if (GET_CODE (op) != REG)
91 if (GET_CODE (SUBREG_REG (op)) != REG)
97 if (GET_CODE (op) != REG)
123 if (GET_CODE (SUBREG_REG (op)) != REG)
129 if (GET_CODE (op) != REG)
151 if (GET_CODE (SUBREG_REG (op)) != REG)
157 if (GET_CODE (op) != REG)
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/
Dregset.h82 #define CLEAR_REGNO_REG_SET(HEAD, REG) bitmap_clear_bit (HEAD, REG) argument
85 #define SET_REGNO_REG_SET(HEAD, REG) bitmap_set_bit (HEAD, REG) argument
88 #define REGNO_REG_SET_P(TO, REG) bitmap_bit_p (TO, REG) argument
Ddf.h728 #define DF_REG_DEF_GET(REG) (df->def_regs[(REG)]) argument
729 #define DF_REG_DEF_CHAIN(REG) (df->def_regs[(REG)]->reg_chain) argument
730 #define DF_REG_DEF_COUNT(REG) (df->def_regs[(REG)]->n_refs) argument
731 #define DF_REG_USE_GET(REG) (df->use_regs[(REG)]) argument
732 #define DF_REG_USE_CHAIN(REG) (df->use_regs[(REG)]->reg_chain) argument
733 #define DF_REG_USE_COUNT(REG) (df->use_regs[(REG)]->n_refs) argument
734 #define DF_REG_EQ_USE_GET(REG) (df->eq_use_regs[(REG)]) argument
735 #define DF_REG_EQ_USE_CHAIN(REG) (df->eq_use_regs[(REG)]->reg_chain) argument
736 #define DF_REG_EQ_USE_COUNT(REG) (df->eq_use_regs[(REG)]->n_refs) argument
/netbsd/src/sys/arch/vax/vsa/
Ddz_vsbus.c76 #define REG(name) short name; short X##name##X; macro
78 REG(csr); /* 00 Csr: control/status register */
79 REG(rbuf); /* 04 Rbuf/Lpr: receive buffer/line param reg. */
80 REG(tcr); /* 08 Tcr: transmit console register */
81 REG(tdr); /* 0C Msr/Tdr: modem status reg/transmit data reg */
82 REG(lpr0); /* 10 Lpr0: */
83 REG(lpr1); /* 14 Lpr0: */
84 REG(lpr2); /* 18 Lpr0: */
85 REG(lpr3); /* 1C Lpr0: */
87 #undef REG
/netbsd/src/external/gpl3/binutils/dist/bfd/
Dcpu-ia64-opc.c467 #define REG IA64_OPND_CLASS_REG macro
494 { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
496 { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
498 { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
500 { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
502 { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
504 { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
506 { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
508 { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
510 { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
[all …]
/netbsd/src/external/gpl3/gdb/dist/bfd/
Dcpu-ia64-opc.c467 #define REG IA64_OPND_CLASS_REG macro
494 { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
496 { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
498 { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
500 { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
502 { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
504 { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
506 { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
508 { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
510 { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
[all …]
/netbsd/src/external/bsd/pcc/dist/pcc/arch/arm/
Dcode.c131 q = block(REG, NIL, NIL, INT, 0, 0); in param_64bit()
159 q = block(REG, NIL, NIL, sym->stype, sym->sdf, sym->sap); in param_64bit()
180 q = block(REG, NIL, NIL, sym->stype, sym->sdf, sym->sap); in param_32bit()
209 q = block(REG, NIL, NIL, INT, 0, 0); in param_double()
241 q = block(REG, NIL, NIL, INT, 0, 0); in param_float()
266 q = block(REG, NIL, NIL, PTR+STRTY, 0, cftnsp->sap); in param_retstruct()
292 q = block(REG, NIL, NIL, INT, 0, 0); in param_struct()
294 p = block(REG, NIL, NIL, INT, 0, 0); in param_struct()
376 q = block(REG, NIL, NIL, INT, 0, 0); in bfcode()
378 p = block(REG, NIL, NIL, INT, 0, 0); in bfcode()
[all …]
/netbsd/src/external/bsd/pcc/dist/pcc/arch/powerpc/
Dcode.c145 q = block(REG, NIL, NIL, INT, 0, 0); in param_64bit()
147 p = block(REG, NIL, NIL, INT, 0, 0); in param_64bit()
152 q = block(REG, NIL, NIL, sym->stype, sym->sdf, sym->sap); in param_64bit()
174 q = block(REG, NIL, NIL, sym->stype, sym->sdf, sym->sap); in param_32bit()
202 q = block(REG, NIL, NIL, ULONGLONG, 0, 0); in param_double()
204 p = block(REG, NIL, NIL, PTR+ULONGLONG, 0, 0); in param_double()
213 p = block(REG, NIL, NIL, in param_double()
222 p = block(REG, NIL, NIL, ULONGLONG, 0, 0); in param_double()
252 q = block(REG, NIL, NIL, INT, 0, 0); in param_float()
254 p = block(REG, NIL, NIL, INT, 0, 0); in param_float()
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/pdp11/
Dpdp11.cc800 else if (GET_CODE (x) == REG) in pdp11_asm_print_operand()
851 case REG: in print_operand_address()
882 else if (GET_CODE (XEXP (addr, 0)) == REG) in print_operand_address()
887 else if (GET_CODE (XEXP (addr, 1)) == REG) in print_operand_address()
892 if (GET_CODE (addr) == REG) in print_operand_address()
907 gcc_assert (GET_CODE (breg) == REG); in print_operand_address()
994 case REG: in pdp11_rtx_costs()
1103 case REG: in pdp11_rtx_costs()
1146 if (GET_CODE (addr) != REG) in pdp11_addr_cost()
1217 case REG: in pdp11_insn_cost()
[all …]
/netbsd/src/external/bsd/pcc/dist/pcc/arch/vax/
Dorder.c58 return( p->n_op == REG || p->n_op == NAME || p->n_op == OREG );
64 if( q->op == INCR && (r=q->left)->op == REG &&
139 (p->op!=REG || !istreg(p->rval)) &&
345 (p->n_left->n_left->n_op!=REG || tlen(p->n_left->n_left)!=sizeof(int) ) ) {
350 (p->n_right->n_left->n_op!=REG || tlen(p->n_right->n_left)!=sizeof(int) ) ) {
355 if( p->n_left->n_op!=REG || tlen(p->n_left)!=sizeof(int) ) {
359 else if( p->n_right->n_op!=REG || tlen(p->n_right)!=sizeof(int) ) {
409 else if( rt == CHAR || rt == UCHAR || rt == SHORT || rt == USHORT || (ro != REG &&
428 if( p->right->op != REG ){
495 ( ro != REG && ro != ICON && ro != NAME && ro != OREG ) ) ){
[all …]
/netbsd/src/external/bsd/pcc/dist/pcc/arch/mips/
Dcode.c136 q = block(REG, NIL, NIL, INCREF(ty), 0, cftnsp->sap); in efcode()
153 p = block(REG, NIL, NIL, INCREF(ty), 0, cftnsp->sap); in efcode()
181 q = block(REG, NIL, NIL, PTR+STRTY, 0, cftnsp->sap); in param_retptr()
206 q = block(REG, NIL, NIL, INT, 0, 0); in param_struct()
208 p = block(REG, NIL, NIL, INT, 0, 0); in param_struct()
244 q = block(REG, NIL, NIL, sym->stype, sym->sdf, sym->sap); in param_64bit()
265 q = block(REG, NIL, NIL, sym->stype, sym->sdf, sym->sap); in param_32bit()
309 q = block(REG, NIL, NIL, LONGLONG, 0, 0); in param_double()
339 q = block(REG, NIL, NIL, INT, 0, 0); in param_float()
413 q = block(REG, NIL, NIL, INT, 0, 0); in bfcode()
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