| /netbsd/src/sys/arch/arm/at91/ |
| D | at91spi.c | 99 #define PUTREG(sc, x, v) \ macro
166 PUTREG(sc, SPI_CR, SPI_CR_SWRST); in at91spi_attach_common()
170 PUTREG(sc, SPI_PDC_BASE + PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); in at91spi_attach_common()
171 PUTREG(sc, SPI_PDC_BASE + PDC_RNCR, 0); in at91spi_attach_common()
172 PUTREG(sc, SPI_PDC_BASE + PDC_RCR, 0); in at91spi_attach_common()
173 PUTREG(sc, SPI_PDC_BASE + PDC_TNCR, 0); in at91spi_attach_common()
174 PUTREG(sc, SPI_PDC_BASE + PDC_TCR, 0); in at91spi_attach_common()
177 PUTREG(sc, SPI_IDR, -1); in at91spi_attach_common()
178 PUTREG(sc, SPI_CSR(0), SPI_CSR_SCBR | SPI_CSR_BITS_8); in at91spi_attach_common()
179 PUTREG(sc, SPI_CSR(1), SPI_CSR_SCBR | SPI_CSR_BITS_8); in at91spi_attach_common()
[all …]
|
| /netbsd/src/sys/dev/ic/ |
| D | smc90cx6.c | 137 #define PUTREG(off, v) bus_space_write_1(bst_r, regs, (off), (v)) macro
172 PUTREG(BAHSTAT, 0); in bah_attach_subr()
174 PUTREG(BAHCMD, BAH_CONF(CONF_LONG)); in bah_attach_subr()
175 PUTREG(BAHCMD, BAH_CLR(CLR_POR|CLR_RECONFIG)); in bah_attach_subr()
275 PUTREG(BAHSTAT, sc->sc_intmask); in bah_reset()
276 PUTREG(BAHCMD, BAH_CONF(CONF_LONG)); in bah_reset()
282 PUTREG(BAHCMD, BAH_CLR(CLR_POR|CLR_RECONFIG)); in bah_reset()
297 PUTREG(BAHCMD, BAH_RXBC(2)); in bah_reset()
298 PUTREG(BAHSTAT, sc->sc_intmask); in bah_reset()
325 PUTREG(BAHSTAT, 0); in bah_stop()
[all …]
|
| /netbsd/src/sys/arch/mips/alchemy/dev/ |
| D | auspi.c | 108 #define PUTREG(sc, x, v) \ macro
160 PUTREG(sc, AUPSC_SPIMSK, SPIMSK_ALL); in auspi_attach()
177 PUTREG(sc, AUPSC_SPIMSK, SPIMSK_NORM); in auspi_configure()
241 PUTREG(sc, AUPSC_SPICFG, reg); in auspi_configure()
280 PUTREG(sc, AUPSC_SPITXRX, data); in auspi_send()
336 PUTREG(sc, AUPSC_SPIPCR, SPIPCR_RC | SPIPCR_TC); in auspi_sched()
341 PUTREG(sc, AUPSC_SPIPCR, SPIPCR_MS); in auspi_sched()
393 PUTREG(sc, AUPSC_SPIEVNT, in auspi_intr()
396 PUTREG(sc, AUPSC_SPIPCR, SPIPCR_RC | SPIPCR_TC); in auspi_intr()
419 PUTREG(sc, AUPSC_SPIEVNT, in auspi_intr()
|
| D | augpio.c | 74 #define PUTREG(x, v) \ macro
78 #define PUTGPIO(x,v) PUTREG(GPIO_BASE + (x), (v))
80 #define PUTGPIO2(x,v) PUTREG(GPIO2_BASE + (x), (v))
|
| D | aurtc.c | 89 #define PUTREG(x,v) (REGVAL(x) = (v)) macro
166 PUTREG(PC_COUNTER_WRITE0, tv.tv_sec); in aurtc_settime()
|
| /netbsd/src/sys/dev/marvell/ |
| D | mvspi.c | 80 #define PUTREG(sc, x, v) \ macro
132 PUTREG(sc, MVSPI_INTCONF_REG, ctl); in mvspi_attach()
243 PUTREG(sc, MVSPI_INTCONF_REG, ctl); in mvspi_configure()
273 PUTREG(sc, MVSPI_CTRL_REG, (sc->sc_transfer->st_slave << 2)); in mvspi_assert()
278 PUTREG(sc, MVSPI_CTRL_REG, ctl); in mvspi_assert()
286 PUTREG(sc, MVSPI_CTRL_REG, ctl); in mvspi_deassert()
317 PUTREG(sc, MVSPI_CTRL_REG, ctl); in mvspi_sched()
326 PUTREG(sc, MVSPI_DATAOUT_REG, byte); in mvspi_sched()
|
| /netbsd/src/sys/arch/mips/atheros/dev/ |
| D | argpio.c | 92 #define PUTREG(sc, o, v) bus_space_write_4(sc->sc_st, sc->sc_sh, o, v) macro
202 PUTREG(sc, GPIO_CR, reg); in argpio_attach()
229 PUTREG(sc, GPIO_CR, reg); in argpio_ctl()
244 PUTREG(sc, GPIO_DO, reg); in argpio_write()
267 PUTREG(sc, GPIO_CR, in argpio_reset_pressed()
281 PUTREG(sc, GPIO_CR, GETREG(sc, GPIO_CR) & ~INTR(sc->sc_rstpin)); in argpio_intr()
|
| D | arspi.c | 133 #define PUTREG(sc, o, v) bus_space_write_4(sc->sc_st, sc->sc_sh, o, v) macro
310 PUTREG(sc, ARSPI_REG_OPCODE, SPIFLASH_CMD_RDSR); in arspi_sched()
316 PUTREG(sc, ARSPI_REG_OPCODE, SPIFLASH_CMD_WREN); in arspi_sched()
322 PUTREG(sc, ARSPI_REG_DATA, job->job_data); in arspi_sched()
325 PUTREG(sc, ARSPI_REG_OPCODE, job->job_opcode | in arspi_sched()
341 PUTREG(sc, ARSPI_REG_CTL, ctl); in arspi_sched()
|