1 /* $NetBSD: mmu_51.h,v 1.4 2024/02/08 20:11:56 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 2023 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jeremy Cooper and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _M68K_MMU_51_H_ 33 #define _M68K_MMU_51_H_ 34 35 /* 36 * Translation table structures for the 68851 MMU. 37 * 38 * The 68851 MMU (as well as the 68030's built-in MMU) are pretty flexible and 39 * can use a 1, 2, 3, or 4-level tree structure and a number of page sizes. 40 * 41 * The logical address format is defined as: 42 * 43 * 31 0 44 * | | | | | | | 45 * SSSSSSSS AAAAAAAAAA BBBBBBBBBB CCCCCCCCCC DDDDDDDDDD PPPPPPPPPPPPPP 46 * Initial A Index B Index C Index D Index Page Offset 47 * Shift 48 * 49 * The Initial Shift, and number of A, B, C, and D index bits are defined 50 * in the Translation Control register. Once the MMU encounters a tree 51 * level where the number of index bits is 0, tree traversal stops. The 52 * values of IS + TIA + TIB + TIC + TID + page offset must equal 32. For 53 * example, for a 2-level arrangment using 4KB pages where all 32-bits of 54 * the address are significant: 55 * 56 * IS TIA TIB TIC TID page 57 * 0 + 10 + 10 + 0 + 0 + 12 == 32 58 */ 59 60 /* 61 * The 68851 has 3 descriptor formats: 62 * 63 * Long Table Descriptors (8 byte) 64 * Short Table Descriptors (4 byte) 65 * Page Descriptors (4 byte) 66 * 67 * These occupy the lower 2 bits of each descriptor and the root pointers. 68 */ 69 #define DT51_INVALID 0 70 #define DT51_PAGE 1 /* points to a page */ 71 #define DT51_SHORT 2 /* points to a short entry table */ 72 #define DT51_LONG 3 /* points to a long entry table */ 73 74 /* 75 * Long Format Table Descriptor 76 * 77 * 63 48 78 * +---+---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 79 * |L/U| LIMIT | 80 * +---+---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 81 * | RAL | WAL |SG | S | 0 | 0 | 0 | 0 | U |WP | DT | 82 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 83 * | TABLE PHYSICAL ADDRESS (BITS 31-16) | 84 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 85 * | TABLE PHYSICAL ADDRESS (15-4) | UNUSED | 86 * +---.---.---.---.---.---.---.---.---.---.---.---+---.---.---.---+ 87 * 15 0 88 * 89 * DT is either 2 or 3, depending on what next table descriptor format is. 90 */ 91 struct mmu51_ldte { /* 'dte' stands for 'descriptor table entry' */ 92 uint32_t ldte_attr; 93 uint32_t ldte_addr; 94 }; 95 #define DTE51_ADDR __BITS(4,31) /* table address mask */ 96 #define DTE51_LOWER __BIT(31) /* L: Index limit is lower limit */ 97 #define DTE51_LIMIT __BITS(16,30) /* L: Index limit */ 98 #define DTE51_RAL __BITS(13,15) /* L: Read Access Level */ 99 #define DTE51_WAL __BITS(10,12) /* L: Write Access Level */ 100 #define DTE51_SG __BIT(9) /* L: Shared Globally */ 101 #define DTE51_S __BIT(8) /* L: Supervisor protected */ 102 #define DTE51_U __BIT(3) /* Used */ 103 #define DTE51_WP __BIT(2) /* Write Protected */ 104 105 /* 106 * Short Format Table Descriptor 107 * 108 * 31 16 109 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 110 * | TABLE PHYSICAL BASE ADDRESS (BITS 31-16) | 111 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 112 * | TABLE PHYSICAL BASE ADDRESS (15-4) | U |WP | DT | 113 * +---.---.---.---.---.---.---.---.---.---.---.---+---+---+---.---+ 114 * 15 0 115 * 116 * DT is either 2 or 3, depending on what next table descriptor format is. 117 */ 118 119 /* 120 * Long Format Page Descriptor (Level A table only) 121 * 122 * 63 48 123 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 124 * | UNUSED | 125 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 126 * | RAL | WAL |SG | S | G |CI | L | M | U |WP |DT (01)| 127 * +---.---.---+---.---.---+---+---+---+---+---+---+---+---+---.---+ 128 * | PAGE PHYSICAL ADDRESS (BITS 31-16) | 129 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 130 * | PAGE PHYS. ADDRESS (15-8) | UNUSED | 131 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 132 * 15 0 133 * 134 * N.B. Unused bits of the page address (if the page size is larger 135 * than 256 bytes) can be used as software-defined PTE bits. 136 */ 137 struct mmu51_lpte { /* 'pte' stands for 'page table entry' */ 138 uint32_t lpte_attr; 139 uint32_t lpte_addr; 140 }; 141 #define PTE51_ADDR __BITS(8,31) /* page address mask */ 142 #define PTE51_RAL __BITS(13,15) /* L: Read Access Level */ 143 #define PTE51_WAL __BITS(10,12) /* L: Write Access Level */ 144 #define PTE51_SG __BIT(9) /* L: Shared Globally */ 145 #define PTE51_S __BIT(8) /* L: Supervisor protected */ 146 #define PTE51_G __BIT(7) /* Gate allowed */ 147 #define PTE51_CI __BIT(6) /* Cache inhibit */ 148 #define PTE51_L __BIT(5) /* Lock entry */ 149 #define PTE51_M __BIT(4) /* Modified */ 150 #define PTE51_U __BIT(3) /* Used */ 151 #define PTE51_WP __BIT(2) /* Write Protected */ 152 153 /* 154 * Short Format Page Descriptor 155 * 156 * 31 16 157 * +---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---+ 158 * | PAGE PHYSICAL BASE ADDRESS (BITS 31-16) | 159 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 160 * | PAGE PHYS. BASE ADDRESS (15-8)| G |CI | L | M | U |WP |DT (01)| 161 * +---.---.---.---.---.---.---.---+---+---+---+---+---+---+---.---+ 162 * 15 0 163 * 164 * N.B. Unused bits of the page address (if the page size is larger 165 * than 256 bytes) can be used as software-defined PTE bits. 166 */ 167 168 /* 169 * MMU registers (and the sections in the 68851 manual that 170 * describe them). 171 */ 172 173 /* 174 * 5.1.4 -- Root Pointer 175 * (and also 6.1.1) 176 * 177 * This is a 64-bit register. The upper 32 bits contain configuration 178 * information, and the lower 32 bits contain the A table address. 179 * Bits 3-0 of the address must be 0. The root pointer is essentially 180 * a long format table descriptor with only the U/L, limit, and SG bits. 181 * 182 * The 68851 has 3 root pointers: 183 * 184 * CRP CPU root pointer, for user accesses 185 * SRP Supervisor root pointer 186 * DRP DMA root pointer, for IOMMU functionality (not on '030) 187 * 188 * Selection of root pointer is as follows: 189 * 190 * FC3 FC2 SRE Root pointer used 191 * 0 0 0 CRP 192 * 0 0 1 CRP 193 * 0 1 0 CRP 194 * 0 1 1 SRP 195 * 1 x x DRP 196 */ 197 struct mmu51_rootptr { 198 unsigned long rp_attr; /* Lower/Upper Limit and access flags */ 199 unsigned long rp_addr; /* Physical Base Address */ 200 }; 201 202 /* 203 * 6.1.2 -- PMMU Cache Status (PCSR) (16-bit) 204 */ 205 #define PCSR51_F __BIT(15) /* Flush(ed) */ 206 #define PCSR51_LW __BIT(14) /* Lock Warning */ 207 #define PCSR51_TA __BITS(0,2) /* Task Alias (not '030) */ 208 209 /* 210 * 6.1.3 -- Translation Control (TCR) (32-bit) 211 */ 212 #define TCR51_E __BIT(31) /* Enable translation */ 213 #define TCR51_SRE __BIT(25) /* Supervisor Root Enable */ 214 #define TCR51_FCL __BIT(24) /* Function Code Lookup */ 215 #define TCR51_PS __BITS(20,23) /* Page Size (see below) */ 216 #define TCR51_IS __BITS(16,19) /* Initial Shift */ 217 #define TCR51_TIA __BITS(12,15) /* Table A Index bits */ 218 #define TCR51_TIB __BITS(8,11) /* Table B Index bits */ 219 #define TCR51_TIC __BITS(4,7) /* Table C Index bits */ 220 #define TCR51_TID __BITS(0,3) /* Table D Index bits */ 221 222 /* 223 * Astute readers will note that the value in the PS field is 224 * log2(PAGE_SIZE). 225 */ 226 #define TCR51_PS_256 __SHIFTIN(0x8, TCR51_PS) 227 #define TCR51_PS_512 __SHIFTIN(0x9, TCR51_PS) 228 #define TCR51_PS_1K __SHIFTIN(0xa, TCR51_PS) 229 #define TCR51_PS_2K __SHIFTIN(0xb, TCR51_PS) 230 #define TCR51_PS_4K __SHIFTIN(0xc, TCR51_PS) 231 #define TCR51_PS_8K __SHIFTIN(0xd, TCR51_PS) 232 #define TCR51_PS_16K __SHIFTIN(0xe, TCR51_PS) 233 #define TCR51_PS_32K __SHIFTIN(0xf, TCR51_PS) 234 235 /* 236 * 6.1.4 -- Current Access Level (8-bit) 237 * 6.1.5 -- Validate Access Level 238 */ 239 #define CAL51_AL __BITS(5,7) 240 241 /* 242 * 6.1.6 -- Stack Change Control (8-bit) 243 */ 244 245 /* 246 * 6.1.7 -- Access Control (16-bit) 247 */ 248 #define AC51_MC __BIT(7) /* Module Control */ 249 #define AC51_ALC __BITS(4,5) /* Access Level Control */ 250 #define AC51_MDS __BITS(0,1) /* Module Descriptor Size */ 251 252 /* 253 * 6.1.8 -- PMMU Status Register (PSR) (16-bit) 254 */ 255 #define PSR51_B __BIT(15) /* Bus Error */ 256 #define PSR51_L __BIT(14) /* Limit Violation */ 257 #define PSR51_S __BIT(13) /* Supervisor Violation */ 258 #define PSR51_A __BIT(12) /* Access Level Violation */ 259 #define PSR51_W __BIT(11) /* Write Protected */ 260 #define PSR51_I __BIT(10) /* Invalid */ 261 #define PSR51_M __BIT(9) /* Modified */ 262 #define PSR51_G __BIT(8) /* Gate */ 263 #define PSR51_C __BIT(7) /* Globally Shareable */ 264 #define PSR51_N __BITS(0,2) /* Number of levels */ 265 266 #ifdef _KERNEL 267 extern unsigned int protorp[2]; 268 269 void mmu_load_urp51(paddr_t); 270 void mmu_load_urp20hp(paddr_t); /* for convenience */ 271 #endif /* _KERNEL */ 272 273 #endif /* _M68K_MMU_51_H_ */ 274