1 /* $NetBSD: psl.h,v 1.9 2018/02/08 09:05:18 dholland Exp $ */ 2 3 /* $OpenBSD: psl.h,v 1.6 1999/11/25 18:29:01 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 1999-2004 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _HPPA_PSL_H_ 32 #define _HPPA_PSL_H_ 33 34 /* 35 * Reference: 36 * 1. PA-RISC 1.1 Architecture and Instruction Set Manual 37 * Hewlett Packard, 3rd Edition, February 1994; Part Number 09740-90039 38 */ 39 40 /* 41 * Processor Status Word Bit Positions (in PA-RISC bit order) 42 */ 43 #define PSW_Y_POS (0) 44 #define PSW_Z_POS (1) 45 #define PSW_SS_POS (3) /* Reserved, Software-defined */ 46 #define PSW_W_POS (4) 47 #define PSW_E_POS (5) 48 #define PSW_S_POS (6) 49 #define PSW_T_POS (7) 50 #define PSW_H_POS (8) 51 #define PSW_L_POS (9) 52 #define PSW_N_POS (10) 53 #define PSW_X_POS (11) 54 #define PSW_B_POS (12) 55 #define PSW_C_POS (13) 56 #define PSW_V_POS (14) 57 #define PSW_M_POS (15) 58 #define PSW_CB_POS (16) 59 #define PSW_O_POS (24) 60 #define PSW_G_POS (25) 61 #define PSW_F_POS (26) 62 #define PSW_R_POS (27) 63 #define PSW_Q_POS (28) 64 #define PSW_P_POS (29) 65 #define PSW_D_POS (30) 66 #define PSW_I_POS (31) 67 68 #define PSW_BITS "\020\001I\002D\003P\004Q\005R\006F\007G\010O" \ 69 "\021M\022V\023C\024B\025X\026N\027L\030H" \ 70 "\031T\032S\033E\034W\037Z\040Y" 71 72 /* 73 * Processor Status Word Bit Values 74 */ 75 #define PSW_Y (1 << (31-PSW_Y_POS)) /* Data Debug Trap Disable */ 76 #define PSW_Z (1 << (31-PSW_Z_POS)) /* Instruction Debug Trap Disable */ 77 #define PSW_SS (1 << (31-PSW_SS_POS)) /* Reserved; Software Single-Step */ 78 #define PSW_W (1 << (31-PSW_W_POS)) /* 64bit address decode enable */ 79 #define PSW_E (1 << (31-PSW_E_POS)) /* Little Endian Memory Access Enable */ 80 #define PSW_S (1 << (31-PSW_S_POS)) /* Secure Interval Timer */ 81 #define PSW_T (1 << (31-PSW_T_POS)) /* Taken Branch Trap Enable */ 82 #define PSW_H (1 << (31-PSW_H_POS)) /* Higher-privilege Transfer Trap Enable */ 83 #define PSW_L (1 << (31-PSW_L_POS)) /* Lower-privilege Transfer Trap Enable */ 84 #define PSW_N (1 << (31-PSW_N_POS)) /* Nullify */ 85 #define PSW_X (1 << (31-PSW_X_POS)) /* Data Memory Break Disable */ 86 #define PSW_B (1 << (31-PSW_B_POS)) /* Taken Branch */ 87 #define PSW_C (1 << (31-PSW_C_POS)) /* Instruction Address Translation Enable */ 88 #define PSW_V (1 << (31-PSW_V_POS)) /* Divide Step Correction */ 89 #define PSW_M (1 << (31-PSW_M_POS)) /* High-priority Machine Check Mask */ 90 #define PSW_CB (1 << (31-PSW_CB_POS)) /* Carry/Borrow Bits */ 91 #define PSW_O (1 << (31-PSW_O_POS)) /* Force strong ordering (2.0) */ 92 #define PSW_G (1 << (31-PSW_G_POS)) /* Debug Trap Enable */ 93 #define PSW_F (1 << (31-PSW_F_POS)) /* Performance Monitor Interrupt Unmask */ 94 #define PSW_R (1 << (31-PSW_R_POS)) /* Recover Counter Enable */ 95 #define PSW_Q (1 << (31-PSW_Q_POS)) /* Interrupt State Collection Enable */ 96 #define PSW_P (1 << (31-PSW_P_POS)) /* Protection Identifier Validation Enable */ 97 #define PSW_D (1 << (31-PSW_D_POS)) /* Data Address Translation Enable */ 98 #define PSW_I (1 << (31-PSW_I_POS)) /* External Interrupt, Power Failure 99 Interrupt, and Low-Priority Machine 100 Check Interrupt unmask */ 101 102 /* 103 * Frequently Used PSW Values 104 */ 105 #define RESET_PSW (PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 106 #define PSW_MBS (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I) 107 #define PSW_MBZ (PSW_Y | PSW_Z | PSW_S | PSW_X | PSW_M | PSW_R) 108 109 #endif /* _HPPA_PSL_H_ */ 110