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Searched refs:PCADDR (Results 1 – 22 of 22) sorted by relevance

/netbsd/src/external/gpl3/gdb/dist/sim/iq2000/
Dsim-main.h53 PCADDR get_h_pc (SIM_CPU *);
54 void set_h_pc (SIM_CPU *, PCADDR);
55 void do_syscall (SIM_CPU *, PCADDR);
56 void do_break (SIM_CPU *, PCADDR);
Diq2000.c42 fetch_str (SIM_CPU *current_cpu, PCADDR pc, DI addr) in fetch_str()
55 do_syscall (SIM_CPU *current_cpu, PCADDR pc) in do_syscall()
138 do_break (SIM_CPU *current_cpu, PCADDR pc) in do_break()
198 PCADDR
205 set_h_pc (SIM_CPU *cpu, PCADDR addr) in set_h_pc()
Dmloop.in47 extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
/netbsd/src/external/gpl3/gdb/dist/sim/frv/
Dfrv-sim.h739 void frv_itrap (SIM_CPU *, PCADDR, USI, int);
744 USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
854 void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
876 void frvbf_load_quad_GR (SIM_CPU *, PCADDR, SI, SI);
877 void frvbf_load_quad_FRint (SIM_CPU *, PCADDR, SI, SI);
878 void frvbf_load_quad_CPR (SIM_CPU *, PCADDR, SI, SI);
879 void frvbf_store_quad_GR (SIM_CPU *, PCADDR, SI, SI);
880 void frvbf_store_quad_FRint (SIM_CPU *, PCADDR, SI, SI);
881 void frvbf_store_quad_CPR (SIM_CPU *, PCADDR, SI, SI);
893 USI frvbf_read_imem_USI (SIM_CPU *, PCADDR);
Dmemory.c177 static PCADDR
178 fr400_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, in fr400_check_insn_read_address()
192 static PCADDR
193 fr500_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, in fr500_check_insn_read_address()
220 static PCADDR
221 fr550_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, in fr550_check_insn_read_address()
241 static PCADDR
242 check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask) in check_insn_read_address()
664 frvbf_read_imem_USI (SIM_CPU *current_cpu, PCADDR vpc) in frvbf_read_imem_USI()
Dfrv.c776 frvbf_load_quad_GR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix) in frvbf_load_quad_GR()
805 frvbf_store_quad_GR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix) in frvbf_store_quad_GR()
831 frvbf_load_quad_FRint (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix) in frvbf_load_quad_FRint()
860 frvbf_store_quad_FRint (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix) in frvbf_store_quad_FRint()
881 frvbf_load_quad_CPR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix) in frvbf_load_quad_CPR()
910 frvbf_store_quad_CPR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix) in frvbf_store_quad_CPR()
Dsim-main.h113 void frvbf_model_branch (SIM_CPU *, PCADDR, int hint);
Dtraps.c113 frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset) in frv_itrap()
303 frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field) in frv_rett()
676 SIM_CPU *current_cpu, PCADDR address, SI regno, int size, int is_float in frvbf_check_recovering_store()
Dmloop.in45 extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
Dcache.c350 PCADDR pc = CPU_PC_GET (current_cpu); in read_data_from_memory()
Dprofile.c1016 frvbf_model_branch (SIM_CPU *current_cpu, PCADDR target, int hint) in frvbf_model_branch()
/netbsd/src/external/gpl3/gdb/dist/sim/common/
Dgenmloop.sh342 PCADDR pc, int fast_p)
369 @prefix@_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
384 @prefix@_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
535 @prefix@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
709 @prefix@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
921 PCADDR pc;
1072 SEM_BRANCH_TYPE br_type, PCADDR new_pc)
1136 PCADDR pc = cur_abuf->addr;
1205 PCADDR pbb_br_npc = 0;
Dcgen-defs.h85 typedef IADDR PCADDR; typedef
DChangeLog-20214264 * cgen-defs.h (PCADDR,CIA): Define in terms of IADDR.
4268 (SEM_BRANCH_INIT): PCADDR->IADDR.
4270 * cgen-scache.c (scache_lookup,scache_lookup_or_alloc): PCADDR->IADDR.
4625 * cgen-trace.c (trace_extract): Use %lx for PCADDR.
/netbsd/src/external/gpl3/gdb/dist/sim/m32r/
Dmloop2.in53 emit_par_finish (SIM_CPU *current_cpu, PCADDR pc, SCACHE *sc,
73 emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
86 emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
99 emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
128 emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
165 emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
177 emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
Dmloopx.in53 emit_par_finish (SIM_CPU *current_cpu, PCADDR pc, SCACHE *sc,
73 emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
86 emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
99 emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
128 emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
165 emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
177 emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
Dm32r-sim.h205 USI m32r_trap (SIM_CPU *, PCADDR, int);
Dmloop.in49 extract16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
65 extract32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
Dtraps.c188 m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num) in m32r_trap()
DChangeLog-20211128 * traps.c (sim_engine_invalid_insn): PCADDR->IADDR.
/netbsd/src/external/gpl3/gdb/dist/sim/lm32/
Dmloop.in39 extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
/netbsd/src/external/gpl3/gdb/dist/sim/cris/
Dmloop.in53 extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,