Home
last modified time | relevance | path

Searched refs:OP0 (Results 1 – 25 of 27) sorted by relevance

12

/netbsd/src/external/gpl3/gdb/dist/include/opcode/
Dh8300.h1565 #define DO_MOVA1(TYPE, OP0, OP1) \ argument
1566 …{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8,…
1567 …{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9,…
1568 …{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA,…
1569 …{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB,…
1570 …{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC,…
1571 …{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD,…
1573 …{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8,…
1574 …{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9,…
1575 …{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA,…
[all …]
Dtic6x-opcode-table.h41 #define OP0() 0, { { 0, 0, false, 0, 0, 0, 0 } } macro
1042 OP0(),
1204 OP0(),
2112 OP0(),
2286 OP0(),
2707 OP0(),
2721 OP0(),
3453 OP0(),
3458 OP0(),
3595 #undef OP0
/netbsd/src/external/gpl3/binutils/dist/include/opcode/
Dh8300.h1565 #define DO_MOVA1(TYPE, OP0, OP1) \ argument
1566 …{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8,…
1567 …{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9,…
1568 …{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA,…
1569 …{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB,…
1570 …{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC,…
1571 …{O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD,…
1573 …{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8,…
1574 …{O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9,…
1575 …{O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA,…
[all …]
Dtic6x-opcode-table.h41 #define OP0() 0, { { 0, 0, false, 0, 0, 0, 0 } } macro
1042 OP0(),
1204 OP0(),
2112 OP0(),
2286 OP0(),
2707 OP0(),
2721 OP0(),
3453 OP0(),
3458 OP0(),
3595 #undef OP0
/netbsd/src/external/gpl3/binutils/dist/opcodes/
Daarch64-tbl.h31 #define OP0() {} macro
3620 CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
3621 CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
3630 PAC_INSN ("retaa", 0xd65f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
3631 PAC_INSN ("retab", 0xd65f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
3632 PAC_INSN ("eretaa", 0xd69f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
3633 PAC_INSN ("eretab", 0xd69f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
3809 FLAGMANIP_INSN ("xaflag", 0xd500403f, 0xffffffff, 0, OP0 (), {}, 0),
3810 FLAGMANIP_INSN ("axflag", 0xd500405f, 0xffffffff, 0, OP0 (), {}, 0),
4239 _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
[all …]
/netbsd/src/external/gpl3/gdb/dist/opcodes/
Daarch64-tbl.h31 #define OP0() {} macro
3711 CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
3712 CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
3721 PAUTH_INSN ("retaa", 0xd65f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
3722 PAUTH_INSN ("retab", 0xd65f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
3723 PAUTH_INSN ("eretaa", 0xd69f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
3724 PAUTH_INSN ("eretab", 0xd69f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
3900 FLAGMANIP_INSN ("xaflag", 0xd500403f, 0xffffffff, 0, OP0 (), {}, 0),
3901 FLAGMANIP_INSN ("axflag", 0xd500405f, 0xffffffff, 0, OP0 (), {}, 0),
4343 _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/s390/
Dvx-builtins.md546 ; Store bytes in OP1 from OP0 with the highest indexed byte to be
547 ; stored from OP0 given by OP2
Ds390-builtins.def2912 …tor element contains the corresponding byte-reversed vector element of the input vector in OP0. */
2937 /* Returns a vector with the elements of the input vector OP0 in reversed order. */
/netbsd/src/external/gpl3/gcc/dist/gcc/config/rx/
Drx.md782 Likewise if both operands are registers but OP1 == OP0. */
/netbsd/src/external/gpl3/gcc/dist/gcc/
Dtree.def1061 If OFF > 0, the last VS - OFF elements of vector OP0 are concatenated to
DChangeLog-20123035 (mips_get_unaligned_mem): Require OP0 to be a BLKmode memory,
6465 use the mode of OP0 to count the number of significant bits.
6482 used when forcing OP0 into a register. Update the call to
6486 Assume that OP0 contains the full field. Simplify the memory offset
6489 Remove WARNED and fix long lines. Assert that the processed OP0
6512 Assume that OP0 contains the full field. Simplify the memory offset
6513 calculation. Assert that the processed OP0 has an integral mode.
27381 * tree-ssa-forwprop.c (simplify_bitwise_binary): Simplify (A & B) OP0
27382 (C & B) to (A OP0) & B.
DChangeLog-19991818 that is needed when OP0 is in a register.
3848 (expand_expr, case ARRAY_REF): If OP0 is in a register, put it in
13095 register instead of OP0.
DChangeLog-200826528 constant outside the natural range of OP0's type.
27418 constant outside the natural range of OP0's type.
DChangeLog9561 * expmed.cc (extract_integral_bit_field): If OP0 is a hard
DFSFChangeLog.1111145 * optabs.c (expand_abs): When OP0 and TARGET are the same
DChangeLog-201718257 Remove assertion that OP0 has a scalar integer mode.
18269 that OP0 has a scalar integer mode. Use as_a <scalar_int_mode>
DChangeLog.tree-ssa9904 make sure OP0 is a suitable constant before trying to fold it.
DChangeLog-200611284 (derive_constant_upper_bound): Handle OP0 - CST in unsigned types
DChangeLog-20019601 (expand_expr, case COMPONENT_EXPR): Always copy OP0 when we need
DChangeLog-200314027 * expr.c (expand_expr, case COMPONENT_REF): If reg, copy OP0 to MEM
DChangeLog-201129168 * expr.c (expand_expr_real_2) <CASE_CONVERT>: If OP0 is a constant,
/netbsd/src/external/gpl3/gcc/dist/gcc/config/i386/
Dsse.md7541 /* NB: SSE can only concatenate OP0 and OP3 to OP0. */
20918 /* NB: SSE can only concatenate OP0 and OP1 to OP0. */
/netbsd/src/external/gpl3/gcc/dist/gcc/doc/
Dgccint.info32301 'rtx maybe_gen_NAME (I1, I2, ..., OP0, OP1, ...)'
32304 instance of it using the operand values given by OP0, OP1, and so
32307 'rtx gen_NAME (I1, I2, ..., OP0, OP1, ...)'
38491 *OP0, rtx *OP1, bool OP0_PRESERVE_VALUE)
38498 conversions. CODE is the initial comparison code and OP0 and OP1
38501 to change the value of OP0 since the value might be used in RTXs
39482 machine_mode MODE, rtx OP0, rtx OP1, rtx *QUOT, rtx *REM)
43792 rtx_insn **GEN_SEQ, int CODE, tree OP0, tree OP1)
43800 OP0 and OP1.
43803 **GEN_SEQ, rtx PREV, int CMP_CODE, tree OP0, tree OP1, int
[all …]
/netbsd/src/external/gpl3/gdb/dist/bfd/
DChangeLog-02033836 PLT,OP0,OP1,OP2,ASM_EXPAND,ASM_SIMPLIFY}.
/netbsd/src/external/gpl3/binutils/dist/bfd/
DChangeLog-02033836 PLT,OP0,OP1,OP2,ASM_EXPAND,ASM_SIMPLIFY}.

12