1 /* $NetBSD: sbd_tr2.h,v 1.4 2024/02/08 20:30:39 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _SBD_TR2_PRIVATE 33 #error "Don't include this file except for TR2 implementation" 34 #endif /* !_SBD_TR2_PRIVATE */ 35 36 #ifndef _EWS4800MIPS_SBD_TR2_H_ 37 #define _EWS4800MIPS_SBD_TR2_H_ 38 /* 39 * EWS4800/350 (TR2) specific system board definition 40 */ 41 42 /* ROM */ 43 #define TR2_ROM_FONT_ADDR 0xbfc0ec00 44 #define TR2_ROM_FONT_SIZE ((0x7f - 0x20) * 24 * sizeof(int16_t)) 45 46 #define TR2_ROM_KEYMAP_NORMAL ((uint8_t *)0xbfc12d6c) 47 #define TR2_ROM_KEYMAP_SHIFTED ((uint8_t *)0xbfc12dec) 48 #define TR2_ROM_KEYMAP_CONTROL ((uint8_t *)0xbfc12e6c) 49 #define TR2_ROM_KEYMAP_CAPSLOCK ((uint8_t *)0xbfc12eec) 50 #define TR2_ROM_KBD_TYPE 0xbfc0fe04 /* [d0 00 00 01] used by kbmskbreset. */ 51 52 #define TR2_ROM_PUTC ((void (*)(int, int, int))0xbfc04f28) 53 #define TR2_ROM_GETC ((int (*)(void))0xbfc11fa0) 54 55 /* System board I/O devices */ 56 #define TR2_PICNIC_ADDR 0xbb000000 57 #define TR2_KBMS_ADDR 0xbb010000 58 #define TR2_SIO_ADDR 0xbb011000 59 #define TR2_NVSRAM_ADDR 0xbb020000 60 #define TR2_NVSRAM_SIZE 0x00004000 61 #define TR2_FDC_ADDR 0xbb030000 62 #define TR2_LPT_ADDR 0xbb040000 63 #define TR2_SCSI_ADDR 0xbb050000 64 #define TR2_ETHER_ADDR 0xbb060000 65 #define TR2_MEMC_ADDR 0xbfa00000 66 #define TR2_NABI_ADDR 0xbfb00000 67 #define TR2_GAFB_ADDR 0xf0000000 68 #define TR2_GAFB_SIZE 0x08000000 69 #define TR2_GACTRL_ADDR 0xf5f00000 70 #define TR2_GACTRL_SIZE 0x1000 71 72 #define SOFTRESET_REG ((volatile uint32_t *)0xbfb00000) 73 #define POWEROFF_REG ((volatile uint8_t *)0xbb004000) 74 #define UPS_STATUS_REG ((volatile uint8_t *)0xbb004008) /* mask 0xffffffbb, 0x4 */ 75 76 #define LED_TF_REG ((volatile uint8_t *)0xbb006000) /* 0/1 (Red)*/ 77 #define TF_ERROR_CODE ((volatile uint8_t *)0xbb006004) /* 1-255 */ 78 79 #define BUZZER_REG ((volatile uint8_t *)0xbb007000) 80 81 /* NABI */ 82 #define NABI0_CTRL_REG ((volatile uint32_t *)0xbfb00000) 83 #define NABI1_CTRL_REG ((volatile uint32_t *)0xbfb00004) 84 #define NABI2_CTRL_REG ((volatile uint32_t *)0xbfb00008) 85 #define NABI0_INTR_REG ((volatile uint32_t *)0xbfb00010) 86 #define NABI1_INTR_REG ((volatile uint32_t *)0xbfb00018) /* VME */ 87 #define NABI2_INTR_REG ((volatile uint32_t *)0xbfb0001c) 88 89 /* 90 * PICNIC (interrupt controller) 91 */ 92 #define PICNIC_INT0_STATUS_REG ((volatile uint8_t *)0xbb000000) 93 #define PICNIC_INT2_STATUS_REG ((volatile uint8_t *)0xbb000004) 94 #define PICNIC_INT4_STATUS_REG ((volatile uint8_t *)0xbb000008) 95 #define PICNIC_INT5_STATUS_REG ((volatile uint8_t *)0xbb000010) 96 #define PICNIC_NMI_REG ((volatile uint8_t *)0xbb000014) 97 98 #define PICNIC_INT0_MASK_REG ((volatile uint8_t *)0xbb001000) 99 #define PICNIC_INT2_MASK_REG ((volatile uint8_t *)0xbb001004) 100 #define PICNIC_INT4_MASK_REG ((volatile uint8_t *)0xbb001008) 101 #define PICNIC_INT5_MASK_REG ((volatile uint8_t *)0xbb001010) 102 /* Interrupt source */ 103 #define PICNIC_INT_FDDLPT 0x80 104 #define PICNIC_INT_ETHER 0x40 105 #define PICNIC_INT_SCSI 0x20 106 #define PICNIC_INT_SERIAL 0x04 107 #define PICNIC_INT_KBMS 0x01 108 #define PICNIC_INT_CLOCK 0x01 109 /* 110 * 76543210 111 * ||| | +-- keyboard, mouse 112 * ||| +-----serial 113 * ||+--------SCSI 114 * |+---------ether 115 * +----------FDC, printer 116 *0xbb00 UX IPL mips int 117 * 1000 0x80 0x00 7 INT0 118 * 1004 0x60 0x00 65 INT2 119 * 1008 0x05 0x00 2 0 INT4 120 * 1010 0x01 0x01 0 Clock INT5 121 */ 122 123 /* SIO0 Z85C30 */ 124 #define KBD_STATUS ((volatile uint8_t *)0xbb010000) 125 #define KBD_DATA ((volatile uint8_t *)0xbb010004) 126 #define MOUSE_STATUS ((volatile uint8_t *)0xbb010008) 127 #define MOUSE_DATA ((volatile uint8_t *)0xbb01000c) 128 /* SIO1 Z85C30 */ 129 #define SIOA_STATUS ((volatile uint8_t *)0xbb011008) 130 #define SIOA_RDATA ((volatile uint8_t *)0xbb01100c) 131 #define SIOB_STATUS ((volatile uint8_t *)0xbb011000) 132 #define SIOB_RDATA ((volatile uint8_t *)0xbb011004) 133 134 /* ETHER i82589 */ 135 /* read operation invokes channel attention. */ 136 #define ETHER_SETADDR_REG ((volatile uint32_t *)0xbb060000) 137 138 /* DCC (DMA controller. Parallel port and FDD use this.) */ 139 struct DCC { 140 uint32_t addr; /* DMA address */ 141 uint32_t cnt; /* transfer count */ 142 uint32_t ctrl; /* DMA status/command */ 143 uint32_t drm; 144 } __attribute__((__packed__)); 145 146 /* FDD uPD72065 (80track ready) */ 147 #define FDC_DMA ((volatile struct DCC *)0xbb030000) 148 #define FDC_STATUS ((volatile uint8_t *)0xbb030010) 149 #define FDC_DATA ((volatile uint8_t *)0xbb030014) 150 151 /* LPT */ 152 #define LPT_DMA (((volatile struct DCC *)0xbb040000) 153 #define LPT_COUNT ((volatile uint8_t *)0xbb040010) 154 #define LPT_STRR ((volatile uint8_t *)0xbb040011) 155 156 /* NVSRAM MK48T08B-15 (word aligned byte access) */ 157 /* 0, 4, 8, c */ 158 #define NVSRAM_SIGNATURE 0xbb020000 159 /* 10, 14 18 1c */ 160 #define NVSRAM_MACHINEID 0xbb020010 161 #define NVSRAM_ETHERADDR ((uint8_t *)0xbb021008) 162 /* 2000, 2004, 2008, 200c */ 163 #define NVSRAM_CDUMP_ADDR ((uint8_t *)0xbb022000) 164 #define NVSRAM_DUMPDEV_1XXX 0xbb022020 165 #define NVSRAM_DUMPDEV_2XXX 0xbb022040 166 /* 2050, 2054, 2058, 205c */ 167 #define NVSRAM_TF_SCRATCH_ADDR 0xbb022050 168 #if 0 169 /* kbd */ 170 #define NVSRAM_KBD??? 0xbb0220a0 /* 0x90 */ 171 #endif 172 #define NVSRAM_TF_TESTDATA1 0xbb023000 173 #define NVSRAM_TF_TESTDATA2 0xbb023004 174 #define NVSRAM_KEYMAP ((uint8_t *)0xbb023014) /* scratch */ 175 #define NVSRAM_TF_PROGRESS ((uint8_t *)0xbb02301c) 176 #define NVSRAM_BEV_ROM 32 /* Exception from ROM routine */ 177 178 #define NVSRAM_KBDCONNECT ((uint8_t *)0xbb023010) 179 #define HAS_KBD() (*NVSRAM_KBDCONNECT != 255) 180 #define NVSRAM_CONSTYPE ((uint8_t *)0xbb023020) 181 #define IS_FBCONS() (*NVSRAM_CONSTYPE == 0) 182 #define NVSRAM_GA 0xbb023008 183 #define HAS_GA 0 184 #define NVSRAM_TF_RESULT_HI 0xbb023024 185 #define NVSRAM_TF_RESULT_LO 0xbb023028 186 #define NVSRAM_IPLMODE ((uint8_t *)0xbb02302c) 187 /* 188 * 0: Normal mode 189 * 1: ERROR continue mode 190 * 2: Details mode 191 * 3: LOOP mode 192 */ 193 #define NVSRAM_BOOTDEV ((uint8_t *)0xbb023030) 194 #define NVSRAM_BOOTUNIT ((uint8_t *)0xbb023034) 195 196 /* V1 is memory area information */ 197 #define NVSRAM_1STBOOT_ARG_V1_3 ((uint8_t *)0xbb023048) /* 24-31 */ 198 #define NVSRAM_1STBOOT_ARG_V1_2 ((uint8_t *)0xbb02304c) /* 16-23 */ 199 #define NVSRAM_1STBOOT_ARG_V1_1 ((uint8_t *)0xbb023050) /* 8 -15 */ 200 #define NVSRAM_1STBOOT_ARG_V1_0 ((uint8_t *)0xbb023054) /* 0 - 7 */ 201 #define NVSRAM_1STBOOT_ARG_V0 ((uint8_t *)0xbb023058) 202 203 #define NVSRAM_SIMM_3_2 ((uint8_t *)0xbb023050) 204 #define NVSRAM_SIMM_1_0 ((uint8_t *)0xbb023054) 205 #define SIMM_16M 0x1 206 #define SIMM_32M 0x2 207 208 #define NVSRAM_RTCADDR ((uint8_t *)0xbb027fe0) 209 210 /* Graphic adapter */ 211 #include <machine/gareg.h> 212 213 /* 214 * VME (350/380) 215 */ 216 #define VME_ADDR 0xf8000000 217 #define VME_32_ADDR 0xf8000000 218 #define VME_32_SIZE 0x07000000 219 #define VME_BUFFER_ADDR 0xff000000 220 #define VME_BUFFER_SIZE 0x00800000 221 #define VME_24_ADDR 0xff800000 222 #define VME_24_SIZE 0x007f0000 223 #define VME_SHORTIO_ADDR 0xffff0000 224 #define VME_SHORTIO_SIZE 0x00010000 225 226 #endif /* !_EWS4800MIPS_SBD_TR2_H_ */ 227