Searched refs:MSR (Results 1 – 25 of 55) sorted by relevance
123
50 #define MSR CPU.spregs[1] macro72 #define C_rd ((MSR & 0x4) >> 2)73 #define C_wr(D) MSR = (D ? MSR | 0x80000004 : MSR & 0x7FFFFFFB)
394 MSR = MSR | BIP_MASK;564 MSR = MSR | INTR_EN_MASK;572 MSR = MSR & ~BIP_MASK;623 MSR = MSR | BIP_MASK;
103 MSR = 0; in set_initial_gprs()
78 kgdbregs[MSR] &= ~PSL_BE; in kgdb_trap_glue()83 kgdbregs[MSR] &= ~PSL_SE; in kgdb_trap_glue()86 kgdbregs[MSR] |= PSL_SE; in kgdb_trap_glue()
98 ld [R_fdc + FDC_REG_MSR], R_msr ! get chip MSR reg addr115 ldub [R_msr], %l7 ! get MSR value141 ldub [R_msr], %l7 ! get MSR value
189 ld [R_fdc + FDC_REG_MSR], R_msr ! get chip MSR reg addr212 ldub [R_msr], %l7 ! get MSR value249 ldub [R_msr], %l7 ! get MSR value
40 #define MSR 37 macro
104 msreg old_msr = MSR; in perform_oea_interrupt()119 MSR = new_msr; in perform_oea_interrupt()
145 if (MSR & msr_e500_spu_enable) { \
342 #define MSR cpu_registers(processor)->msr macro
338 if ((MSR & (msr_floating_point_exception_mode_0 \
111 #define MSR 0xc /* RW - Misc. setup register */ macro
592 #define MSR 6 macro612 tmp = INP(MSR); in Init16550()
22 options XS_BEE3 # MSR/BeCube BEE3 system
21 defflag XS_BEE3 # MSR/BeCube BEE3
35 options XS_BEE3 # MSR/BeCube BEE3 system
90 MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC
115 MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific