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Searched refs:MIPS_SR_INT_IE (Results 1 – 20 of 20) sorted by relevance

/netbsd/src/sys/arch/mips/mips/
Dspl.S84 or v1, MIPS_SR_INT_IE #
85 xor v1, MIPS_SR_INT_IE # clear interrupt enable bit
141 or v0, v1, MIPS_SR_INT_IE #
142 xor v0, MIPS_SR_INT_IE # clear interrupt enable bit
175 or v1, MIPS_SR_INT_IE # make sure interrupts are on
182 or v1, v0, MIPS_SR_INT_IE #
183 xor v1, MIPS_SR_INT_IE # clear interrupt enable bit
202 or v0, v1, MIPS_SR_INT_IE #
203 xor v0, MIPS_SR_INT_IE # clear interrupt enable bit
222 or v0, v1, MIPS_SR_INT_IE #
[all …]
Dcache_r5k.c232 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); in r4600v1_pdcache_wbinv_range_32()
252 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); in r4600v2_pdcache_wbinv_range_32()
302 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); in r4600v1_pdcache_inv_range_32()
322 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); in r4600v2_pdcache_inv_range_32()
358 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); in r4600v1_pdcache_wb_range_32()
378 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); in r4600v2_pdcache_wb_range_32()
440 mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE); in r5k_sdcache_wbinv_range()
Dlocore.S78 and k0, ~MIPS_SR_INT_IE
195 or v0, MIPS_SR_INT_IE
236 and t0, MIPS_SR_INT_IE
331 and t1, t0, MIPS_SR_INT_IE
334 and t1, t0, MIPS_SR_INT_IE
393 and v0, t1, MIPS_SR_INT_IE # assert interrupts are on
397 and v0, t1, MIPS_SR_INT_IE # assert interrupts are on
472 and v0, t1, MIPS_SR_INT_IE
Dmips_fpu.c115 … : "r"(tf->tf_regs[_R_SR] & (MIPS_SR_COP_1_BIT|MIPS3_SR_FR|MIPS_SR_KX|MIPS_SR_INT_IE)), in mips_fpu_state_save()
246 …: "r"(tf->tf_regs[_R_SR] & (MIPS_SR_COP_1_BIT|MIPS3_SR_FR|MIPS_SR_KX|MIPS_SR_INT_IE)), "n"(MIPS_CO… in mips_fpu_state_load()
Dlocore_mips3.S177 andi v1, v0, MIPS_SR_INT_IE
200 andi v1, v0, MIPS_SR_INT_IE
592 and t1, t0, ~(MIPS_SR_INT_IE)
621 and t1, t0, ~(MIPS_SR_INT_IE)
658 and t2, t0, MIPS_SR_INT_IE # disable interrupts
Dmips_softint.c116 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); in softint_process()
Dlocore_mips1.S511 or v0, v1, MIPS_SR_INT_IE
528 and t0, MIPS_SR_INT_IE
590 or v0, MIPS_SR_INT_IE
794 or v0, MIPS_SR_INT_IE # make sure intrs are still on
796 li v0, MIPS_SR_INT_IE # reenable intrs
849 and v0, v1, MIPS_SR_INT_IE # clear interrupt enable
885 or t0, MIPS_SR_INT_IE # enable interrupts
964 li t0, MIPS_SR_INT_IE
968 ori t0, MIPS_SR_INT_IE # turn on IEc, enable intr.
Dvm_machdep.c155 KASSERTMSG(pcb2->pcb_context.val[_L_SR] & MIPS_SR_INT_IE, in cpu_lwp_fork()
DmipsX_subr.S810 li v1, MIPS_SR_INT_IE << T_BREAK # make a mask of T_BREAK
813 and v1, MIPS_SR_INT_IE # restrict to IE bit
1196 and t0, MIPS_SR_INT_IE
1246 xor v0, MIPS_SR_INT_IE # disable interrupts
1276 or v0, MIPS_SR_INT_IE
1605 and v0, v1, MIPS_SR_INT_IE # clear interrupt enable
1644 or t0, MIPS_SR_INT_IE # enable interrupts
2559 and t0, v1, MIPS_SR_INT_IE
Dmips_machdep.c2147 pcb->pcb_context.val[_L_SR] = MIPS_SR_INT_IE in mips_init_lwp0_uarea()
2376 KASSERT((status & MIPS_SR_INT_IE) == 0); in std_splsw_test()
Dcpu_subr.c966 KASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); in cpu_hatch()
/netbsd/src/sys/arch/evbmips/evbmips/
Dinterrupt.c61 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); in cpu_intr()
66 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); in cpu_intr()
68 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); in cpu_intr()
110 KDASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); in cpu_intr()
/netbsd/src/sys/arch/mips/include/
Dpsl.h48 #define MIPS3_PSL_LOWIPL (MIPS3_INT_MASK | MIPS_SR_INT_IE)
59 MIPS_SR_INT_IE | \
69 #define MIPS1_PSL_LOWIPL (MIPS_INT_MASK | MIPS_SR_INT_IE)
Dcpuregs.h228 #define MIPS_SR_INT_IE 0x00000001 macro
Dasm.h800 ori sr, (MIPS_INT_MASK | MIPS_SR_INT_IE); \
/netbsd/src/sys/arch/arc/
DTODO69 mips_idle: li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
70 machdep.c: curpcb->pcb_context[11] = MIPS_INT_MASK | MIPS_SR_INT_IE;
/netbsd/src/sys/arch/sgimips/sgimips/
Dip22_cache.S53 li v0, ~MIPS_SR_INT_IE /* ints off */ ; \
/netbsd/src/sys/arch/mips/rmi/
Drmixl_spl.S87 ori t0, MIPS_SR_INT_IE # set IE
/netbsd/src/sys/arch/playstation2/playstation2/
Dlocore_machdep.S110 li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
/netbsd/src/sys/arch/arc/isa/
Disabus.c445 cf->sr &= ~MIPS_SR_INT_IE; in isabr_iointr()